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Searched refs:engine_mask (Results 1 – 25 of 25) sorted by relevance

/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_reset.c158 intel_engine_mask_t engine_mask, in i915_do_reset() argument
187 intel_engine_mask_t engine_mask, in g33_do_reset() argument
197 intel_engine_mask_t engine_mask, in g4x_do_reset() argument
233 static int ilk_do_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask, in ilk_do_reset() argument
321 intel_engine_mask_t engine_mask, in __gen6_reset_engines() argument
327 if (engine_mask == ALL_ENGINES) { in __gen6_reset_engines()
333 for_each_engine_masked(engine, gt, engine_mask, tmp) { in __gen6_reset_engines()
342 intel_engine_mask_t engine_mask, in gen6_reset_engines() argument
349 ret = __gen6_reset_engines(gt, engine_mask, retry); in gen6_reset_engines()
522 intel_engine_mask_t engine_mask, in __gen11_reset_engines() argument
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H A Dintel_reset.h26 intel_engine_mask_t engine_mask,
57 int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask);
H A Dintel_gt_types.h262 intel_engine_mask_t engine_mask; member
306 intel_engine_mask_t engine_mask; member
H A Dintel_engine_cs.c790 gt->info.engine_mask &= ~BIT(_VCS(i)); in engine_mask_apply_media_fuses()
810 gt->info.engine_mask &= ~BIT(_VECS(i)); in engine_mask_apply_media_fuses()
840 info->engine_mask &= ~BIT(_CCS(i)); in engine_mask_apply_compute_fuses()
868 if (mask & info->engine_mask) { in engine_mask_apply_copy_fuses()
872 info->engine_mask &= ~mask; in engine_mask_apply_copy_fuses()
891 GEM_BUG_ON(!info->engine_mask); in init_engine_mask()
909 if (__HAS_ENGINE(info->engine_mask, GSC0) && !intel_uc_wants_gsc_uc(&gt->uc)) { in init_engine_mask()
912 info->engine_mask &= ~BIT(GSC0); in init_engine_mask()
933 info->engine_mask &= ~GENMASK(CCS3, CCS0); in init_engine_mask()
935 info->engine_mask |= BIT(_CCS(first_ccs)); in init_engine_mask()
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H A Dintel_gt.c238 intel_engine_mask_t engine_mask) in intel_gt_clear_error_registers() argument
279 for_each_engine_masked(engine, gt, engine_mask, id) in intel_gt_clear_error_registers()
907 gt->info.engine_mask = INTEL_INFO(i915)->platform_engine_mask; in intel_gt_probe_all()
931 gt->info.engine_mask = gtdef->engine_mask; in intel_gt_probe_all()
991 drm_printf(p, "available engines: %x\n", info->engine_mask); in intel_gt_info_print()
H A Dintel_breadcrumbs_types.h49 intel_engine_mask_t engine_mask; member
H A Dintel_gt.h107 intel_engine_mask_t engine_mask);
/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Dscheduler.h150 intel_engine_mask_t engine_mask);
155 intel_engine_mask_t engine_mask,
169 intel_engine_mask_t engine_mask);
H A Dvgpu.c435 intel_engine_mask_t engine_mask) in intel_gvt_reset_vgpu_locked() argument
439 intel_engine_mask_t resetting_eng = dmlr ? ALL_ENGINES : engine_mask; in intel_gvt_reset_vgpu_locked()
443 vgpu->id, dmlr, engine_mask); in intel_gvt_reset_vgpu_locked()
460 if (engine_mask == ALL_ENGINES || dmlr) { in intel_gvt_reset_vgpu_locked()
462 if (engine_mask == ALL_ENGINES) in intel_gvt_reset_vgpu_locked()
H A Dexeclist.c523 intel_engine_mask_t engine_mask) in clean_execlist() argument
529 for_each_engine_masked(engine, vgpu->gvt->gt, engine_mask, tmp) { in clean_execlist()
537 intel_engine_mask_t engine_mask) in reset_execlist() argument
542 for_each_engine_masked(engine, vgpu->gvt->gt, engine_mask, tmp) in reset_execlist()
547 intel_engine_mask_t engine_mask) in init_execlist() argument
549 reset_execlist(vgpu, engine_mask); in init_execlist()
H A Dgvt.h145 int (*init)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
146 void (*clean)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
147 void (*reset)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
508 intel_engine_mask_t engine_mask);
H A Dscheduler.c1048 intel_engine_mask_t engine_mask) in intel_vgpu_clean_workloads() argument
1056 for_each_engine_masked(engine, vgpu->gvt->gt, engine_mask, tmp) { in intel_vgpu_clean_workloads()
1343 intel_engine_mask_t engine_mask) in intel_vgpu_reset_submission() argument
1350 intel_vgpu_clean_workloads(vgpu, engine_mask); in intel_vgpu_reset_submission()
1351 s->ops->reset(vgpu, engine_mask); in intel_vgpu_reset_submission()
1467 intel_engine_mask_t engine_mask, in intel_vgpu_select_submission_ops() argument
1482 interface == 0 && engine_mask != ALL_ENGINES)) in intel_vgpu_select_submission_ops()
1486 s->ops->clean(vgpu, engine_mask); in intel_vgpu_select_submission_ops()
1496 ret = ops[interface]->init(vgpu, engine_mask); in intel_vgpu_select_submission_ops()
H A Dhandlers.c314 intel_engine_mask_t engine_mask = 0; in gdrst_mmio_write() local
322 engine_mask = ALL_ENGINES; in gdrst_mmio_write()
326 engine_mask |= BIT(RCS0); in gdrst_mmio_write()
330 engine_mask |= BIT(VCS0); in gdrst_mmio_write()
334 engine_mask |= BIT(BCS0); in gdrst_mmio_write()
338 engine_mask |= BIT(VECS0); in gdrst_mmio_write()
342 engine_mask |= BIT(VCS1); in gdrst_mmio_write()
348 engine_mask &= vgpu->gvt->gt->info.engine_mask; in gdrst_mmio_write()
352 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); in gdrst_mmio_write()
/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_gpu_error.h274 intel_engine_mask_t engine_mask);
277 intel_engine_mask_t engine_mask) in intel_klog_error_capture() argument
293 intel_engine_mask_t engine_mask, u32 dump_flags);
295 intel_engine_mask_t engine_mask, u32 dump_flags);
354 i915_capture_error_state(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) in i915_capture_error_state() argument
H A Di915_drv.h399 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
704 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id)) argument
705 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
714 __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)
H A Di915_gpu_error.c1679 intel_engine_mask_t engine_mask, in gt_record_engines() argument
1696 ee->hung = engine->mask & engine_mask; in gt_record_engines()
2094 __i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) in __i915_gpu_coredump() argument
2130 gt_record_engines(error->gt, engine_mask, compress, dump_flags); in __i915_gpu_coredump()
2144 i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) in i915_gpu_coredump() argument
2153 dump = __i915_gpu_coredump(gt, engine_mask, dump_flags); in i915_gpu_coredump()
2200 intel_engine_mask_t engine_mask, u32 dump_flags) in i915_capture_error_state() argument
2204 error = i915_gpu_coredump(gt, engine_mask, dump_flags); in i915_capture_error_state()
2252 intel_engine_mask_t engine_mask) in intel_klog_error_capture() argument
2279 error = i915_gpu_coredump(gt, engine_mask, CORE_DUMP_FLAG_NONE); in intel_klog_error_capture()
H A Di915_pci.c814 .engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2) | BIT(GSC0),
H A Dintel_uncore.c2314 emask = uncore->gt->info.engine_mask; in intel_uncore_fw_domains_init()
/openbmc/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_huc.c256 intel_engine_mask_t mask = gt->info.engine_mask; in vcs_supported()
267 GEM_BUG_ON(!gt_is_root(gt) && !gt->info.engine_mask); in vcs_supported()
272 mask = gt->info.engine_mask; in vcs_supported()
H A Dintel_gsc_uc.c110 GEM_BUG_ON(!gt_is_root(gt) && !gt->info.engine_mask); in gsc_engine_supported()
115 mask = gt->info.engine_mask; in gsc_engine_supported()
H A Dintel_guc_submission.c4051 intel_engine_mask_t tmp, mask = b->engine_mask; in guc_irq_enable_breadcrumbs()
4064 intel_engine_mask_t tmp, mask = b->engine_mask; in guc_irq_disable_breadcrumbs()
4097 engine->breadcrumbs->engine_mask |= engine->mask; in guc_init_breadcrumbs()
4799 intel_engine_mask_t engine_mask; in capture_error_state() local
4805 engine_mask = 0; in capture_error_state()
4811 engine_mask |= e->mask; in capture_error_state()
4817 if (!engine_mask) { in capture_error_state()
4820 engine_mask = ~0U; in capture_error_state()
4824 engine_mask = ce->engine->mask; in capture_error_state()
4829 i915_capture_error_state(gt, engine_mask, CORE_DUMP_FLAG_IS_GUC_CAPTURE); in capture_error_state()
H A Dintel_guc_ads.c714 u32 engine_mask = guc_get_capture_engine_mask(&info_map, j); in guc_capture_prep_lists() local
717 if (!engine_mask) { in guc_capture_prep_lists()
/openbmc/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76x02_dfs.c617 u32 engine_mask; in mt76x02_dfs_tasklet() local
641 engine_mask = mt76_rr(dev, MT_BBP(DFS, 1)); in mt76x02_dfs_tasklet()
642 if (!(engine_mask & 0xf)) in mt76x02_dfs_tasklet()
648 if (!(engine_mask & (1 << i))) in mt76x02_dfs_tasklet()
/openbmc/linux/drivers/gpu/drm/i915/selftests/
H A Dmock_gem_device.c230 to_gt(i915)->info.engine_mask = BIT(0); in mock_gem_device()
/openbmc/qemu/hw/intc/
H A Dpnv_xive2.c1144 static uint8_t pnv_xive2_cache_watch_assign(uint64_t engine_mask, in pnv_xive2_cache_watch_assign() argument
1151 if (BIT(i) & engine_mask) { in pnv_xive2_cache_watch_assign()
1173 uint64_t engine_mask = GETFIELD(VC_ENDC_CFG_CACHE_WATCH_ASSIGN, in pnv_xive2_endc_cache_watch_assign() local
1185 val = pnv_xive2_cache_watch_assign(engine_mask, &state); in pnv_xive2_endc_cache_watch_assign()
1443 uint64_t engine_mask = GETFIELD(PC_NXC_PROC_CONFIG_WATCH_ASSIGN, in pnv_xive2_nxc_cache_watch_assign() local
1455 val = pnv_xive2_cache_watch_assign(engine_mask, &state); in pnv_xive2_nxc_cache_watch_assign()