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Searched refs:effective_cs (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c53 for (effective_cs = 0; effective_cs < MAX_CS_NUM; effective_cs++) in ddr3_tip_dynamic_read_leveling()
56 rl_values[effective_cs][bus_num][if_id] = 0; in ddr3_tip_dynamic_read_leveling()
58 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_dynamic_read_leveling()
94 effective_cs, STRESS_NONE, DURATION_SINGLE)); in ddr3_tip_dynamic_read_leveling()
115 (0x301b01 | effective_cs << 2), 0x3c3fef)); in ddr3_tip_dynamic_read_leveling()
214 if_id, effective_cs, bus_num)); in ddr3_tip_dynamic_read_leveling()
225 rl_values[effective_cs][bus_num] in ddr3_tip_dynamic_read_leveling()
265 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_dynamic_read_leveling()
274 data = rl_values[effective_cs][bus_num][if_id]; in ddr3_tip_dynamic_read_leveling()
282 RL_PHY_REG(effective_cs), in ddr3_tip_dynamic_read_leveling()
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H A Dddr3_training_pbs.c73 CRX_PHY_REG(effective_cs) : in ddr3_tip_pbs()
74 CTX_PHY_REG(effective_cs); in ddr3_tip_pbs()
187 (0x54 + effective_cs * 0x10) : in ddr3_tip_pbs()
188 (0x14 + effective_cs * 0x10); in ddr3_tip_pbs()
194 (0x55 + effective_cs * 0x10) : in ddr3_tip_pbs()
195 (0x15 + effective_cs * 0x10); in ddr3_tip_pbs()
247 (0x54 + effective_cs * 0x10) : in ddr3_tip_pbs()
248 (0x14 + effective_cs * 0x10); in ddr3_tip_pbs()
257 (0x55 + effective_cs * 0x10) : in ddr3_tip_pbs()
258 (0x15 + effective_cs * 0x10); in ddr3_tip_pbs()
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H A Dddr3_training.c60 u32 effective_cs = 0; variable
1239 ddr3_tip_calc_cs_mask(dev_num, if_id, effective_cs, in ddr3_tip_freq_set()
1778 if (cs_bitmask != effective_cs) { in ddr3_tip_write_cs_result()
1784 (effective_cs * 0x4), in ddr3_tip_write_cs_result()
1889 WL_PHY_REG(effective_cs), in ddr3_tip_ddr3_reset_phy_regs()
1894 RL_PHY_REG(effective_cs), in ddr3_tip_ddr3_reset_phy_regs()
1899 CRX_PHY_REG(effective_cs), phy_reg3_val)); in ddr3_tip_ddr3_reset_phy_regs()
1903 CTX_PHY_REG(effective_cs), phy_reg1_val)); in ddr3_tip_ddr3_reset_phy_regs()
1907 PBS_TX_BCAST_PHY_REG(effective_cs), 0x0)); in ddr3_tip_ddr3_reset_phy_regs()
1911 PBS_RX_BCAST_PHY_REG(effective_cs), 0)); in ddr3_tip_ddr3_reset_phy_regs()
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H A Dddr3_training_centralization.c94 reg_phy_off = CTX_PHY_REG(effective_cs); in ddr3_tip_centralization()
98 reg_phy_off = CRX_PHY_REG(effective_cs); in ddr3_tip_centralization()
189 effective_cs, pattern_id, in ddr3_tip_centralization()
442 effective_cs, &reg); in ddr3_tip_centralization()
456 effective_cs, reg)); in ddr3_tip_centralization()
512 if ((ddr3_tip_special_rx_run_once_flag & (1 << effective_cs)) == (1 << effective_cs)) in ddr3_tip_special_rx()
515 ddr3_tip_special_rx_run_once_flag |= (1 << effective_cs); in ddr3_tip_special_rx()
627 PBS_RX_PHY_REG(effective_cs, pad_num), in ddr3_tip_special_rx()
637 PBS_RX_PHY_REG(effective_cs, pad_num), in ddr3_tip_special_rx()
651 PBS_RX_PHY_REG(effective_cs, 4), in ddr3_tip_special_rx()
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H A Dddr3_training_ip_engine.c385 (0x3 | (effective_cs << 26)), 0xc000003)); in ddr3_tip_ip_training()
409 delay_between_burst, rd_mode, effective_cs, STRESS_NONE, in ddr3_tip_ip_training()
461 reg_data = PBS_RX_BCAST_PHY_REG(effective_cs); in ddr3_tip_ip_training()
464 reg_data = PBS_TX_BCAST_PHY_REG(effective_cs); in ddr3_tip_ip_training()
475 reg_data = CTX_PHY_REG(effective_cs); in ddr3_tip_ip_training()
479 reg_data = CRX_PHY_REG(effective_cs); in ddr3_tip_ip_training()
890 (effective_cs << 26); in ddr3_tip_load_pattern_to_mem()
897 ODPG_DATA_CTRL_REG, (0x1 | (effective_cs << 26)), in ddr3_tip_load_pattern_to_mem()
1473 CTX_PHY_REG(effective_cs), in ddr3_tip_load_phy_values()
1480 RL_PHY_REG(effective_cs), in ddr3_tip_load_phy_values()
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H A Dddr3_training_leveling.h12 int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,
H A Dddr3_init.h123 extern u32 effective_cs;