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Searched refs:eTSEC (Results 1 – 25 of 41) sorted by relevance

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/openbmc/qemu/hw/net/fsl_etsec/
H A Detsec.h91 struct eTSEC { struct
133 typedef struct eTSEC eTSEC; argument
136 OBJECT_DECLARE_SIMPLE_TYPE(eTSEC, ETSEC_COMMON)
141 void etsec_update_irq(eTSEC *etsec);
143 void etsec_walk_tx_ring(eTSEC *etsec, int ring_nbr);
144 void etsec_walk_rx_ring(eTSEC *etsec, int ring_nbr);
145 ssize_t etsec_rx_ring_write(eTSEC *etsec, const uint8_t *buf, size_t size);
147 void etsec_write_miim(eTSEC *etsec,
152 void etsec_miim_link_status(eTSEC *etsec, NetClientState *nc);
H A Detsec.c56 void etsec_update_irq(eTSEC *etsec) in etsec_update_irq()
79 eTSEC *etsec = opaque; in etsec_read()
109 static void write_tstat(eTSEC *etsec, in write_tstat()
127 static void write_rstat(eTSEC *etsec, in write_rstat()
145 static void write_tbasex(eTSEC *etsec, in write_tbasex()
156 static void write_rbasex(eTSEC *etsec, in write_rbasex()
167 static void write_dmactrl(eTSEC *etsec, in write_dmactrl()
211 eTSEC *etsec = opaque; in etsec_write()
297 eTSEC *etsec = opaque; in etsec_timer_hit()
313 eTSEC *etsec = ETSEC_COMMON(d); in etsec_reset()
[all …]
H A Dmiim.c32 static void miim_read_cycle(eTSEC *etsec) in miim_read_cycle()
64 static void miim_write_cycle(eTSEC *etsec) in miim_write_cycle()
88 void etsec_write_miim(eTSEC *etsec, in etsec_write_miim()
133 void etsec_miim_link_status(eTSEC *etsec, NetClientState *nc) in etsec_miim_link_status()
H A Drings.c106 static void read_buffer_descriptor(eTSEC *etsec, in read_buffer_descriptor()
128 static void write_buffer_descriptor(eTSEC *etsec, in write_buffer_descriptor()
150 static void ievent_set(eTSEC *etsec, in ievent_set()
158 static void tx_padding_and_crc(eTSEC *etsec, uint32_t min_frame_len) in tx_padding_and_crc()
175 static void process_tx_fcb(eTSEC *etsec) in process_tx_fcb()
220 static void process_tx_bd(eTSEC *etsec, in process_tx_bd()
322 void etsec_walk_tx_ring(eTSEC *etsec, int ring_nbr) in etsec_walk_tx_ring()
381 static void fill_rx_bd(eTSEC *etsec, in fill_rx_bd()
446 static void rx_init_frame(eTSEC *etsec, const uint8_t *buf, size_t size) in rx_init_frame()
488 ssize_t etsec_rx_ring_write(eTSEC *etsec, const uint8_t *buf, size_t size) in etsec_rx_ring_write()
[all …]
/openbmc/linux/Documentation/networking/device_drivers/ethernet/freescale/
H A Dgianfar.rst14 The eTSEC controller (first included in parts from late 2005 like
34 TSEC (and the extended hash table on the eTSEC) for multicast
35 filtering. On the eTSEC, the exact-match MAC registers are used
/openbmc/linux/Documentation/devicetree/bindings/ptp/
H A Dptp-qoriq.txt5 - compatible Should be "fsl,etsec-ptp" for eTSEC
56 For eTSEC,
59 <1> - eTSEC system clock;
70 will use the eTSEC system clock (for Gianfar) or the MAC system
/openbmc/linux/arch/powerpc/boot/dts/
H A Dxcalibur1501.dts387 /* eTSEC 1 front panel 0 */
393 model = "eTSEC";
437 /* eTSEC 2 front panel 1 */
443 model = "eTSEC";
467 /* eTSEC 3 PICMG2.16 backplane port 0 */
473 model = "eTSEC";
497 /* eTSEC 4 PICMG2.16 backplane port 1 */
503 model = "eTSEC";
H A Dxpedite5200.dts200 model = "eTSEC";
249 model = "eTSEC";
278 model = "eTSEC";
307 model = "eTSEC";
H A Dxpedite5200_xmon.dts204 model = "eTSEC";
253 model = "eTSEC";
282 model = "eTSEC";
311 model = "eTSEC";
H A Dtqm8548.dts164 model = "eTSEC";
217 model = "eTSEC";
245 model = "eTSEC";
273 model = "eTSEC";
H A Dtqm8548-bigflash.dts164 model = "eTSEC";
217 model = "eTSEC";
245 model = "eTSEC";
273 model = "eTSEC";
H A Dxpedite5301.dts367 /* eTSEC 1 */
373 model = "eTSEC";
407 /* eTSEC 2 */
413 model = "eTSEC";
H A Dxpedite5370.dts365 /* eTSEC 1 */
371 model = "eTSEC";
405 /* eTSEC 2 */
411 model = "eTSEC";
H A Dmpc8308rdb.dts146 model = "eTSEC";
178 model = "eTSEC";
H A Dxpedite5330.dts403 /* eTSEC 1 */
409 model = "eTSEC";
443 /* eTSEC 2 */
449 model = "eTSEC";
H A Dsocrates.dts134 model = "eTSEC";
172 model = "eTSEC";
H A Dmpc8308_p1m.dts171 model = "eTSEC";
206 model = "eTSEC";
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dpq3-etsec1-0.dtsi2 * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ]
40 model = "eTSEC";
H A Dpq3-etsec1-3.dtsi2 * PQ3 eTSEC device tree stub [ @ offsets 0x27000 ]
40 model = "eTSEC";
H A Dpq3-etsec1-2.dtsi2 * PQ3 eTSEC device tree stub [ @ offsets 0x26000 ]
40 model = "eTSEC";
H A Dpq3-etsec1-1.dtsi2 * PQ3 eTSEC device tree stub [ @ offsets 0x25000 ]
40 model = "eTSEC";
/openbmc/qemu/docs/system/ppc/
H A Dppce500.rst23 * 1 Freescale Enhanced Triple Speed Ethernet controller (eTSEC)
163 The QEMU ``ppce500`` machine can also dynamically instantiate an eTSEC device
164 if “-device eTSEC” is given to QEMU:
168 -netdev tap,ifname=tap0,script=no,downscript=no,id=net0 -device eTSEC,netdev=net0
/openbmc/u-boot/board/freescale/bsc9131rdb/
H A DREADME27 including IEEE 1588. v2 hardware support and virtualization (eTSEC)
28 . eTSEC 1 supports RGMII/RMII
29 . eTSEC 2 supports RGMII
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dfsl-tsec-phy.txt51 - model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
55 interrupt. For TSEC and eTSEC devices, the first interrupt is
/openbmc/u-boot/board/Arcturus/ucp1020/
H A DREADME12 KSZ9031 (current default for eTSEC 1 and 3)

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