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Searched refs:dwbc (Results 1 – 25 of 25) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dwb.c46 static bool dwb3_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) in dwb3_get_caps() argument
66 void dwb3_config_fc(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb3_config_fc() argument
68 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_config_fc()
88 dwb3_set_stereo(dwbc, &params->stereo_params); in dwb3_config_fc()
91 bool dwb3_enable(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb3_enable() argument
93 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_enable()
94 DC_LOG_DWB("%s dwb3_enabled at inst = %d", __func__, dwbc->inst); in dwb3_enable()
100 dwb3_config_fc(dwbc, params); in dwb3_enable()
103 dwb3_program_hdr_mult(dwbc, params); in dwb3_enable()
104 dwb3_set_gamut_remap(dwbc, params); in dwb3_enable()
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H A Ddcn30_dwb_cm.c270 struct dwbc *dwbc, in dwb3_ogam_set_input_transfer_func() argument
273 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_ogam_set_input_transfer_func()
283 cm_helper_translate_curve_to_hw_format(dwbc->ctx, in dwb3_ogam_set_input_transfer_func()
298 struct dwbc *dwbc, in dwb3_program_gamut_remap() argument
303 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_program_gamut_remap()
353 struct dwbc *dwbc, in dwb3_set_gamut_remap() argument
356 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_set_gamut_remap()
362 dwb3_program_gamut_remap(dwbc, NULL, adjust.gamut_coef_format, CM_GAMUT_REMAP_MODE_BYPASS); in dwb3_set_gamut_remap()
376 dwb3_program_gamut_remap(dwbc, arr_reg_val, in dwb3_set_gamut_remap()
379 dwb3_program_gamut_remap(dwbc, arr_reg_val, in dwb3_set_gamut_remap()
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H A Ddcn30_dwb.h861 struct dwbc base;
874 bool dwb3_enable(struct dwbc *dwbc, struct dc_dwb_params *params);
876 bool dwb3_disable(struct dwbc *dwbc);
878 bool dwb3_update(struct dwbc *dwbc, struct dc_dwb_params *params);
880 bool dwb3_is_enabled(struct dwbc *dwbc);
882 void dwb3_set_stereo(struct dwbc *dwbc,
885 void dwb3_set_new_content(struct dwbc *dwbc,
888 void dwb3_config_fc(struct dwbc *dwbc,
891 void dwb3_set_denorm(struct dwbc *dwbc, struct dc_dwb_params *params);
894 struct dwbc *dwbc,
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H A Ddcn30_hwseq.c253 struct dwbc *dwb; in dcn30_update_writeback()
254 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn30_update_writeback()
270 struct dwbc *dwb; in dcn30_mmhubbub_warmup()
276 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
305 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
328 struct dwbc *dwb; in dcn30_enable_writeback()
331 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn30_enable_writeback()
350 struct dwbc *dwb; in dcn30_disable_writeback()
354 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dcn30_disable_writeback()
373 struct dwbc *dwb; in dcn30_program_all_writeback_pipes_in_tree()
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H A Ddcn30_resource.c1138 if (pool->base.dwbc[i] != NULL) { in dcn30_resource_destruct()
1139 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn30_resource_destruct()
1140 pool->base.dwbc[i] = NULL; in dcn30_resource_destruct()
1233 pool->dwbc[i] = &dwbc30->base; in dcn30_dwbc_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Ddwb.h155 struct dwbc { struct
175 struct dwbc *dwbc, argument
179 struct dwbc *dwbc,
182 bool (*disable)(struct dwbc *dwbc);
185 struct dwbc *dwbc,
189 struct dwbc *dwbc);
192 struct dwbc *dwbc,
196 struct dwbc *dwbc,
201 struct dwbc *dwbc,
208 struct dwbc *dwbc,
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dwb.c50 static bool dwb2_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) in dwb2_get_caps() argument
52 struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc); in dwb2_get_caps()
72 void dwb2_config_dwb_cnv(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb2_config_dwb_cnv() argument
74 struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc); in dwb2_config_dwb_cnv()
99 static bool dwb2_enable(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb2_enable() argument
101 struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc); in dwb2_enable()
121 dwb2_config_dwb_cnv(dwbc, params); in dwb2_enable()
124 dwb2_set_scaler(dwbc, params); in dwb2_enable()
135 bool dwb2_disable(struct dwbc *dwbc) in dwb2_disable() argument
137 struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc); in dwb2_disable()
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H A Ddcn20_dwb.h389 struct dwbc base;
402 bool dwb2_disable(struct dwbc *dwbc);
404 bool dwb2_is_enabled(struct dwbc *dwbc);
406 void dwb2_set_stereo(struct dwbc *dwbc,
409 void dwb2_set_new_content(struct dwbc *dwbc,
412 void dwb2_config_dwb_cnv(struct dwbc *dwbc,
415 void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params);
H A Ddcn20_hwseq.c2224 struct dwbc *dwb; in dcn20_enable_writeback()
2230 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn20_enable_writeback()
2250 struct dwbc *dwb; in dcn20_disable_writeback()
2254 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dcn20_disable_writeback()
2911 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; in dcn20_fpga_init_hw()
H A Ddcn20_resource.c1152 if (pool->base.dwbc[i] != NULL) { in dcn20_resource_destruct()
1153 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); in dcn20_resource_destruct()
1154 pool->base.dwbc[i] = NULL; in dcn20_resource_destruct()
2248 pool->dwbc[i] = &dwbc20->base; in dcn20_dwbc_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dwb.c45 static bool dwb1_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) in dwb1_get_caps() argument
64 static bool dwb1_enable(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb1_enable() argument
66 struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc); in dwb1_enable()
69 dwbc->funcs->disable(dwbc); in dwb1_enable()
81 static bool dwb1_disable(struct dwbc *dwbc) in dwb1_disable() argument
83 struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc); in dwb1_disable()
H A Ddcn10_dwb.h254 struct dwbc base;
/openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dcore_types.h224 struct dwbc *dwbc[MAX_DWB_PIPES]; member
407 struct dwbc *dwbc; member
/openbmc/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_stream.c476 struct dwbc *dwb; in dc_stream_add_writeback()
495 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
516 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn302/
H A Ddcn302_resource.c720 pool->dwbc[i] = &dwbc30->base; in dcn302_dwbc_create()
1060 if (pool->dwbc[i] != NULL) { in dcn302_resource_destruct()
1061 kfree(TO_DCN30_DWBC(pool->dwbc[i])); in dcn302_resource_destruct()
1062 pool->dwbc[i] = NULL; in dcn302_resource_destruct()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn303/
H A Ddcn303_resource.c663 pool->dwbc[i] = &dwbc30->base; in dcn303_dwbc_create()
986 if (pool->dwbc[i] != NULL) { in dcn303_resource_destruct()
987 kfree(TO_DCN30_DWBC(pool->dwbc[i])); in dcn303_resource_destruct()
988 pool->dwbc[i] = NULL; in dcn303_resource_destruct()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_resource.c1108 if (pool->base.dwbc[i] != NULL) { in dcn301_destruct()
1109 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn301_destruct()
1110 pool->base.dwbc[i] = NULL; in dcn301_destruct()
1192 pool->dwbc[i] = &dwbc30->base; in dcn301_dwbc_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn316/
H A Ddcn316_resource.c1438 if (pool->base.dwbc[i] != NULL) { in dcn316_resource_destruct()
1439 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn316_resource_destruct()
1440 pool->base.dwbc[i] = NULL; in dcn316_resource_destruct()
1527 pool->dwbc[i] = &dwbc30->base; in dcn31_dwbc_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn315/
H A Ddcn315_resource.c1440 if (pool->base.dwbc[i] != NULL) { in dcn315_resource_destruct()
1441 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn315_resource_destruct()
1442 pool->base.dwbc[i] = NULL; in dcn315_resource_destruct()
1529 pool->dwbc[i] = &dwbc30->base; in dcn31_dwbc_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn321/
H A Ddcn321_resource.c1425 if (pool->base.dwbc[i] != NULL) { in dcn321_resource_destruct()
1426 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn321_resource_destruct()
1427 pool->base.dwbc[i] = NULL; in dcn321_resource_destruct()
1506 pool->dwbc[i] = &dwbc30->base; in dcn321_dwbc_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_resource.c1512 if (pool->base.dwbc[i] != NULL) { in dcn314_resource_destruct()
1513 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn314_resource_destruct()
1514 pool->base.dwbc[i] = NULL; in dcn314_resource_destruct()
1604 pool->dwbc[i] = &dwbc30->base; in dcn31_dwbc_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_resource.c746 if (pool->base.dwbc[i] != NULL) { in dcn21_resource_destruct()
747 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); in dcn21_resource_destruct()
748 pool->base.dwbc[i] = NULL; in dcn21_resource_destruct()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_resource.c1440 if (pool->base.dwbc[i] != NULL) { in dcn31_resource_destruct()
1441 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn31_resource_destruct()
1442 pool->base.dwbc[i] = NULL; in dcn31_resource_destruct()
1532 pool->dwbc[i] = &dwbc30->base; in dcn31_dwbc_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_resource.c1440 if (pool->base.dwbc[i] != NULL) { in dcn32_resource_destruct()
1441 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn32_resource_destruct()
1442 pool->base.dwbc[i] = NULL; in dcn32_resource_destruct()
1521 pool->dwbc[i] = &dwbc30->base; in dcn32_dwbc_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_hwseq.c328 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; in dcn201_init_hw()