Searched refs:dtpr (Results 1 – 7 of 7) sorted by relevance
269 &mctl_phy->dtpr[0]); in mctl_set_timing_lpddr3()270 writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]); in mctl_set_timing_lpddr3()271 writel(((txs << 6) - 1) | (tcke << 17), &mctl_phy->dtpr[2]); in mctl_set_timing_lpddr3()273 &mctl_phy->dtpr[3]); in mctl_set_timing_lpddr3()274 writel((txp << 1) | (trfc << 17) | 0x800, &mctl_phy->dtpr[4]); in mctl_set_timing_lpddr3()275 writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]); in mctl_set_timing_lpddr3()276 writel(0x0505, &mctl_phy->dtpr[6]); in mctl_set_timing_lpddr3()
643 &mctl_phy->dtpr[0]); in mctl_channel_init()646 &mctl_phy->dtpr[1]); in mctl_channel_init()651 &mctl_phy->dtpr[2]); in mctl_channel_init()
178 u32 dtpr[7]; /* 0x110 */ member
106 u32 dtpr[4]; /* 0x8c DRAM timing parameters register */ member
178 u32 dtpr[3]; member
300 copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, in phy_cfg()331 tmp = readl(&publ->dtpr[1]); in phy_cfg()
266 copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, in phy_cfg()