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Searched refs:drex0 (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Ddmc_init_ddr3.c447 struct exynos5420_dmc *drex0, *drex1; in ddr3_mem_ctrl_init() local
458 drex0 = (struct exynos5420_dmc *)samsung_get_base_dmc_ctrl(); in ddr3_mem_ctrl_init()
545 writel(val, &drex0->phycontrol0); in ddr3_mem_ctrl_init()
551 &drex0->concontrol); in ddr3_mem_ctrl_init()
558 val = readl(&drex0->phystatus); in ddr3_mem_ctrl_init()
564 clrbits_le32(&drex0->concontrol, DFI_INIT_START); in ddr3_mem_ctrl_init()
567 update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3); in ddr3_mem_ctrl_init()
599 &drex0->prechconfig0); in ddr3_mem_ctrl_init()
607 writel(mem->timing_ref, &drex0->timingref); in ddr3_mem_ctrl_init()
609 writel(mem->timing_row, &drex0->timingrow0); in ddr3_mem_ctrl_init()
[all …]
/openbmc/linux/drivers/devfreq/event/
H A Dexynos-ppmu.c76 PPMU_EVENT(drex0-s0),
77 PPMU_EVENT(drex0-s1),