dram_timing1 (reference) in projects: openbmc

Searched refs:dram_timing1 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A D	sdram_gen5.h	`26 u32 dram_timing1; member 85 u32 dram_timing1; member`
/openbmc/u-boot/drivers/ddr/altera/
H A D	sdram_gen5.c	`334 writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1); in sdr_load_regs()`
/openbmc/u-boot/arch/arm/mach-socfpga/
H A D	wrap_sdram_config.c	`33 .dram_timing1 =`