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Searched refs:dram_clk_cfg (Results 1 – 11 of 11) sorted by relevance

/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sunxi_dw.c380 clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); in mctl_sys_init()
385 clrsetbits_le32(&ccm->dram_clk_cfg, in mctl_sys_init()
393 clrsetbits_le32(&ccm->dram_clk_cfg, in mctl_sys_init()
400 mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); in mctl_sys_init()
407 setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); in mctl_sys_init()
H A Ddram_sun8i_a83t.c401 clrbits_le32(&ccm->dram_clk_cfg, 0x01<<31); in mctl_sys_init()
405 clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK, in mctl_sys_init()
408 mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); in mctl_sys_init()
H A Ddram_sun50i_h6.c306 clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET); in mctl_sys_init()
316 writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg); in mctl_sys_init()
317 setbits_le32(&ccm->dram_clk_cfg, DRAM_CLK_UPDATE); in mctl_sys_init()
330 setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET); in mctl_sys_init()
H A Ddram_sun8i_a33.c309 clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK, in mctl_sys_init()
312 mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); in mctl_sys_init()
H A Ddram_sun9i.c292 writel((3 << 12) | (1 << 16), &ccm->dram_clk_cfg); in mctl_sys_init()
296 } while (readl(&ccm->dram_clk_cfg) & (1 << 16)); in mctl_sys_init()
297 setbits_le32(&ccm->dram_clk_cfg, (1 << 31)); in mctl_sys_init()
H A Ddram_sun6i.c37 clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK, in mctl_sys_init()
40 mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); in mctl_sys_init()
H A Ddram_sun8i_a23.c224 setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); in mctl_init()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun9i.h61 u32 dram_clk_cfg; /* 0x484 DRAM (controller) clock config */ member
H A Dclock_sun8i_a83t.h64 u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */ member
H A Dclock_sun50i_h6.h133 u32 dram_clk_cfg; /* 0x800 DRAM clock control */ member
H A Dclock_sun6i.h70 u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */ member