| /openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | dpp.h | 44 struct dpp { struct
162 struct dpp *dpp_base, const struct pwl_params *params);
164 void (*dpp_set_pre_degam)(struct dpp *dpp_base,
167 void (*dpp_program_cm_dealpha)(struct dpp *dpp_base,
171 struct dpp *dpp_base,
174 void (*dpp_read_state)(struct dpp *dpp, struct dcn_dpp_state *s);
176 void (*dpp_reset)(struct dpp *dpp);
178 void (*dpp_set_scaler)(struct dpp *dpp,
182 struct dpp *dpp,
187 struct dpp *dpp,
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_dpp_cm.c | 43 dpp->tf_regs->reg
46 dpp->base.ctx
50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
92 struct dcn10_dpp *dpp, in program_gamut_remap() argument
118 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
119 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
120 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
121 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
129 dpp->base.ctx, in program_gamut_remap()
139 dpp->base.ctx, in program_gamut_remap()
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| H A D | dcn10_dpp.c | 42 dpp->tf_regs->reg
45 dpp->base.ctx
49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
94 void dpp_read_state(struct dpp *dpp_base, in dpp_read_state()
97 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp_read_state() local
125 struct dpp *dpp, in dpp1_get_optimal_number_of_taps() argument
131 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT && in dpp1_get_optimal_number_of_taps()
137 dpp->ctx->dc->debug.max_downscale_src_width != 0 && in dpp1_get_optimal_number_of_taps()
138 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) in dpp1_get_optimal_number_of_taps()
174 if (!dpp->ctx->dc->debug.always_scale) { in dpp1_get_optimal_number_of_taps()
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| H A D | dcn10_dpp_dscl.c | 44 dpp->tf_regs->reg
47 dpp->base.ctx
51 dpp->tf_shift->field_name, dpp->tf_mask->field_name
124 struct dpp *dpp_base, in dpp1_dscl_get_dscl_mode()
158 struct dpp *dpp_base, in dpp1_power_on_dscl()
161 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_power_on_dscl() local
163 if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) { in dpp1_power_on_dscl()
168 if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) { in dpp1_power_on_dscl()
169 dpp->base.ctx->dc->optimized_required = true; in dpp1_power_on_dscl()
170 dpp->base.deferred_reg_writes.bits.disable_dscl = true; in dpp1_power_on_dscl()
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| H A D | dcn10_resource.c | 570 static void dcn10_dpp_destroy(struct dpp **dpp) in dcn10_dpp_destroy() argument
572 kfree(TO_DCN10_DPP(*dpp)); in dcn10_dpp_destroy()
573 *dpp = NULL; in dcn10_dpp_destroy()
576 static struct dpp *dcn10_dpp_create( in dcn10_dpp_create()
580 struct dcn10_dpp *dpp = in dcn10_dpp_create() local
583 if (!dpp) in dcn10_dpp_create()
586 dpp1_construct(dpp, ctx, inst, in dcn10_dpp_create()
588 return &dpp->base; in dcn10_dpp_create()
1111 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn10_acquire_free_pipe_for_layer()
1359 dc->caps.color.dpp.dcn_arch = 1; in dcn10_resource_construct()
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| H A D | dcn10_hw_sequencer.c | 299 struct dpp *dpp = pool->dpps[i]; in dcn10_log_hw_state() local
302 dpp->funcs->dpp_read_state(dpp, &s); in dcn10_log_hw_state()
309 dpp->inst, in dcn10_log_hw_state()
1185 int dpp_id = pipe_ctx->plane_res.dpp->inst; in dcn10_plane_atomic_disconnect()
1227 struct dpp *dpp, in dcn10_plane_atomic_power_down() argument
1238 hws->funcs.dpp_pg_control(hws, dpp->inst, false); in dcn10_plane_atomic_power_down()
1243 dpp->funcs->dpp_reset(dpp); in dcn10_plane_atomic_power_down()
1252 hws->funcs.dpp_root_clock_control(hws, dpp->inst, false); in dcn10_plane_atomic_power_down()
1262 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn10_plane_atomic_disable() local
1269 dpp->funcs->dpp_dppclk_control(dpp, false, false); in dcn10_plane_atomic_disable()
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| H A D | dcn10_dpp.h | 30 #define TO_DCN10_DPP(dpp)\ argument
31 container_of(dpp, struct dcn10_dpp, base)
1357 struct dpp base;
1382 struct dpp *dpp_base,
1386 struct dpp *dpp_base,
1393 struct dpp *dpp_base,
1408 struct dpp *dpp_base,
1412 struct dpp *dpp_base,
1416 struct dpp *dpp_base,
1420 struct dpp *dpp_base,
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_dpp_cm.c | 34 dpp->tf_regs->reg
37 dpp->base.ctx
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
44 struct dpp *dpp_base) in dpp3_enable_cm_block()
46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_enable_cm_block() local
57 static enum dc_lut_mode dpp30_get_gamcor_current(struct dpp *dpp_base) in dpp30_get_gamcor_current()
62 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_get_gamcor_current() local
81 struct dpp *dpp_base, in dpp3_program_gammcor_lut()
87 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_gammcor_lut() local
130 struct dpp *dpp_base, in dpp3_power_on_gamcor_lut()
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| H A D | dcn30_dpp.c | 34 dpp->tf_regs->reg
37 dpp->base.ctx
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
44 void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s) in dpp30_read_state()
46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_read_state() local
55 struct dpp *dpp_base, in dpp3_program_post_csc()
60 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_post_csc() local
100 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11; in dpp3_program_post_csc()
101 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_POST_CSC_C11; in dpp3_program_post_csc()
102 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12; in dpp3_program_post_csc()
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| H A D | dcn30_dpp.h | 30 #define TO_DCN30_DPP(dpp)\ argument
31 container_of(dpp, struct dcn3_dpp, base)
561 struct dpp base;
587 struct dpp *dpp_base, const struct pwl_params *params);
590 struct dpp *dpp_base,
593 void dpp30_read_state(struct dpp *dpp_base,
597 struct dpp *dpp,
602 struct dpp *dpp_base,
610 struct dpp *dpp_base,
614 struct dpp *dpp_base,
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_dpp_cm.c | 37 dpp->tf_regs->reg
43 dpp->base.ctx
47 dpp->tf_shift->field_name, dpp->tf_mask->field_name
51 struct dpp *dpp_base) in dpp2_enable_cm_block()
53 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_enable_cm_block() local
65 struct dpp *dpp_base, in dpp2_degamma_ram_inuse()
70 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_degamma_ram_inuse() local
86 struct dpp *dpp_base, in dpp2_program_degamma_lut()
93 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_program_degamma_lut() local
117 struct dpp *dpp_base, in dpp2_set_degamma_pwl()
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| H A D | dcn20_dpp.c | 42 dpp->tf_regs->reg
45 dpp->base.ctx
49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
51 void dpp20_read_state(struct dpp *dpp_base, in dpp20_read_state()
54 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp20_read_state() local
76 struct dpp *dpp_base, in dpp2_power_on_obuf()
79 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_power_on_obuf() local
91 struct dpp *dpp_base, in dpp2_dummy_program_input_lut()
96 struct dpp *dpp_base, in dpp2_cnv_setup()
103 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_cnv_setup() local
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_dpp.c | 35 dpp->tf_regs->reg
38 dpp->base.ctx
42 dpp->tf_shift->field_name, dpp->tf_mask->field_name
45 struct dpp *dpp_base, in dpp201_cnv_setup()
52 struct dcn201_dpp *dpp = TO_DCN201_DPP(dpp_base); in dpp201_cnv_setup() local
184 struct dpp *dpp, in dpp201_get_optimal_number_of_taps() argument
190 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT && in dpp201_get_optimal_number_of_taps()
195 dpp->ctx->dc->debug.max_downscale_src_width != 0 && in dpp201_get_optimal_number_of_taps()
196 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) in dpp201_get_optimal_number_of_taps()
240 if (!dpp->ctx->dc->debug.always_scale) { in dpp201_get_optimal_number_of_taps()
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| H A D | dcn201_resource.c | 619 static void dcn201_dpp_destroy(struct dpp **dpp) in dcn201_dpp_destroy() argument
621 kfree(TO_DCN201_DPP(*dpp)); in dcn201_dpp_destroy()
622 *dpp = NULL; in dcn201_dpp_destroy()
625 static struct dpp *dcn201_dpp_create( in dcn201_dpp_create()
629 struct dcn201_dpp *dpp = in dcn201_dpp_create() local
632 if (!dpp) in dcn201_dpp_create()
635 if (dpp201_construct(dpp, ctx, inst, in dcn201_dpp_create()
637 return &dpp->base; in dcn201_dpp_create()
639 kfree(dpp); in dcn201_dpp_create()
1019 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn201_acquire_free_pipe_for_layer()
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| H A D | dcn201_dpp.h | 30 #define TO_DCN201_DPP(dpp)\ argument
31 container_of(dpp, struct dcn201_dpp, base)
58 struct dpp base;
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| H A D | dcn201_hwseq.c | 285 struct dpp *dpp = res_pool->dpps[i]; in dcn201_init_hw() local
287 dpp->funcs->dpp_reset(dpp); in dcn201_init_hw()
305 struct dpp *dpp = res_pool->dpps[i]; in dcn201_init_hw() local
311 pipe_ctx->plane_res.dpp = dpp; in dcn201_init_hw()
312 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn201_init_hw()
313 hubp->mpcc_id = dpp->inst; in dcn201_init_hw()
376 int dpp_id = pipe_ctx->plane_res.dpp->inst; in dcn201_plane_atomic_disconnect()
560 pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes( in dcn201_set_cursor_attribute()
561 pipe_ctx->plane_res.dpp, attributes); in dcn201_set_cursor_attribute()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_dpp.c | 146 struct dcn3_dpp *dpp, in dpp32_construct() argument
153 dpp->base.ctx = ctx; in dpp32_construct()
155 dpp->base.inst = inst; in dpp32_construct()
156 dpp->base.funcs = &dcn32_dpp_funcs; in dpp32_construct()
157 dpp->base.caps = &dcn32_dpp_cap; in dpp32_construct()
159 dpp->tf_regs = tf_regs; in dpp32_construct()
160 dpp->tf_shift = tf_shift; in dpp32_construct()
161 dpp->tf_mask = tf_mask; in dpp32_construct()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn301/ |
| H A D | dcn301_resource.c | 705 static void dcn301_dpp_destroy(struct dpp **dpp) in dcn301_dpp_destroy() argument
707 kfree(TO_DCN20_DPP(*dpp)); in dcn301_dpp_destroy()
708 *dpp = NULL; in dcn301_dpp_destroy()
711 static struct dpp *dcn301_dpp_create(struct dc_context *ctx, uint32_t inst) in dcn301_dpp_create()
713 struct dcn3_dpp *dpp = in dcn301_dpp_create() local
716 if (!dpp) in dcn301_dpp_create()
719 if (dpp3_construct(dpp, ctx, inst, in dcn301_dpp_create()
721 return &dpp->base; in dcn301_dpp_create()
724 kfree(dpp); in dcn301_dpp_create()
1438 dc->caps.color.dpp.dcn_arch = 1; in dcn301_resource_construct()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn302/ |
| H A D | dcn302_resource.c | 535 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst) in dcn302_dpp_create()
537 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); in dcn302_dpp_create() local
539 if (!dpp) in dcn302_dpp_create()
542 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn302_dpp_create()
543 return &dpp->base; in dcn302_dpp_create()
546 kfree(dpp); in dcn302_dpp_create()
1235 dc->caps.color.dpp.dcn_arch = 1; in dcn302_resource_construct()
1236 dc->caps.color.dpp.input_lut_shared = 0; in dcn302_resource_construct()
1237 dc->caps.color.dpp.icsc = 1; in dcn302_resource_construct()
1238 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr in dcn302_resource_construct()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn303/ |
| H A D | dcn303_resource.c | 495 static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst) in dcn303_dpp_create()
497 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); in dcn303_dpp_create() local
499 if (!dpp) in dcn303_dpp_create()
502 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn303_dpp_create()
503 return &dpp->base; in dcn303_dpp_create()
506 kfree(dpp); in dcn303_dpp_create()
1159 dc->caps.color.dpp.dcn_arch = 1; in dcn303_resource_construct()
1160 dc->caps.color.dpp.input_lut_shared = 0; in dcn303_resource_construct()
1161 dc->caps.color.dpp.icsc = 1; in dcn303_resource_construct()
1162 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr in dcn303_resource_construct()
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| /openbmc/linux/arch/sparc/vdso/ |
| H A D | vma.c | 250 struct page *dp, **dpp = NULL; in init_vdso_image() local
290 dpp = kcalloc(dnpages, sizeof(struct page *), GFP_KERNEL); in init_vdso_image()
291 vvar_mapping.pages = dpp; in init_vdso_image()
293 if (!dpp) in init_vdso_image()
300 dpp[0] = dp; in init_vdso_image()
318 if (dpp != NULL) { in init_vdso_image()
320 if (dpp[i] != NULL) in init_vdso_image()
321 __free_page(dpp[i]); in init_vdso_image()
323 kfree(dpp); in init_vdso_image()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
| H A D | dcn21_resource.c | 499 static struct dpp *dcn21_dpp_create( in dcn21_dpp_create()
503 struct dcn20_dpp *dpp = in dcn21_dpp_create() local
506 if (!dpp) in dcn21_dpp_create()
509 if (dpp2_construct(dpp, ctx, inst, in dcn21_dpp_create()
511 return &dpp->base; in dcn21_dpp_create()
514 kfree(dpp); in dcn21_dpp_create()
1448 dc->caps.color.dpp.dcn_arch = 1; in dcn21_resource_construct()
1449 dc->caps.color.dpp.input_lut_shared = 0; in dcn21_resource_construct()
1450 dc->caps.color.dpp.icsc = 1; in dcn21_resource_construct()
1451 dc->caps.color.dpp.dgam_ram = 1; in dcn21_resource_construct()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn316/ |
| H A D | dcn316_resource.c | 901 static void dcn31_dpp_destroy(struct dpp **dpp) in dcn31_dpp_destroy() argument
903 kfree(TO_DCN20_DPP(*dpp)); in dcn31_dpp_destroy()
904 *dpp = NULL; in dcn31_dpp_destroy()
907 static struct dpp *dcn31_dpp_create( in dcn31_dpp_create()
911 struct dcn3_dpp *dpp = in dcn31_dpp_create() local
914 if (!dpp) in dcn31_dpp_create()
917 if (dpp3_construct(dpp, ctx, inst, in dcn31_dpp_create()
919 return &dpp->base; in dcn31_dpp_create()
922 kfree(dpp); in dcn31_dpp_create()
1766 dc->caps.color.dpp.dcn_arch = 1; in dcn316_resource_construct()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/ |
| H A D | dcn314_resource.c | 912 .dpp = true,
957 static void dcn31_dpp_destroy(struct dpp **dpp) in dcn31_dpp_destroy() argument
959 kfree(TO_DCN20_DPP(*dpp)); in dcn31_dpp_destroy()
960 *dpp = NULL; in dcn31_dpp_destroy()
963 static struct dpp *dcn31_dpp_create( in dcn31_dpp_create()
967 struct dcn3_dpp *dpp = in dcn31_dpp_create() local
970 if (!dpp) in dcn31_dpp_create()
973 if (dpp3_construct(dpp, ctx, inst, in dcn31_dpp_create()
975 return &dpp->base; in dcn31_dpp_create()
978 kfree(dpp); in dcn31_dpp_create()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn315/ |
| H A D | dcn315_resource.c | 905 static void dcn31_dpp_destroy(struct dpp **dpp) in dcn31_dpp_destroy() argument
907 kfree(TO_DCN20_DPP(*dpp)); in dcn31_dpp_destroy()
908 *dpp = NULL; in dcn31_dpp_destroy()
911 static struct dpp *dcn31_dpp_create( in dcn31_dpp_create()
915 struct dcn3_dpp *dpp = in dcn31_dpp_create() local
918 if (!dpp) in dcn31_dpp_create()
921 if (dpp3_construct(dpp, ctx, inst, in dcn31_dpp_create()
923 return &dpp->base; in dcn31_dpp_create()
926 kfree(dpp); in dcn31_dpp_create()
1879 dc->caps.color.dpp.dcn_arch = 1; in dcn315_resource_construct()
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