Searched refs:dpll_reg (Results 1 – 4 of 4) sorted by relevance
| /openbmc/u-boot/drivers/clk/aspeed/ |
| H A D | clk_ast2500.c | 102 u32 dpll_reg = readl(&scu->d_pll_param); in ast2500_get_dpll_rate() local
105 const ulong num = (dpll_reg & 0xff); in ast2500_get_dpll_rate()
106 const ulong denum = (dpll_reg >> 8) & 0x1f; in ast2500_get_dpll_rate()
107 const ulong post_div = (dpll_reg >> 13) & 0x3f; in ast2500_get_dpll_rate()
108 const ulong od_div = (dpll_reg >> 19) & 0x7; in ast2500_get_dpll_rate()
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| /openbmc/linux/drivers/video/fbdev/intelfb/ |
| H A D | intelfbhw.c | 1281 u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg, pipe_stat_reg; in intelfbhw_program_mode() local
1312 dpll_reg = DPLL_B; in intelfbhw_program_mode()
1336 dpll_reg = DPLL_A; in intelfbhw_program_mode()
1396 tmp = INREG(dpll_reg); in intelfbhw_program_mode()
1398 OUTREG(dpll_reg, tmp); in intelfbhw_program_mode()
1405 OUTREG(dpll_reg, *dpll); in intelfbhw_program_mode()
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| /openbmc/linux/drivers/gpu/drm/gma500/ |
| H A D | cdv_intel_display.c | 220 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; in cdv_dpll_set_clock_cdv() local
227 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS); in cdv_dpll_set_clock_cdv()
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| /openbmc/linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_display.c | 362 i915_reg_t dpll_reg; in vlv_wait_port_ready() local
370 dpll_reg = DPLL(0); in vlv_wait_port_ready()
374 dpll_reg = DPLL(0); in vlv_wait_port_ready()
379 dpll_reg = DPIO_PHY_STATUS; in vlv_wait_port_ready()
383 if (intel_de_wait_for_register(dev_priv, dpll_reg, in vlv_wait_port_ready()
388 intel_de_read(dev_priv, dpll_reg) & port_mask, in vlv_wait_port_ready()
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