Searched refs:dml_input (Results 1 – 5 of 5) sorted by relevance
373 …k_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_u… in dcn30_fpu_update_soc_for_wm_a()374 …r_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_ex… in dcn30_fpu_update_soc_for_wm_a()375 ….soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us; in dcn30_fpu_update_soc_for_wm_a()413 …k_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_u… in dcn30_fpu_calculate_wm_and_dlg()437 …k_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_u… in dcn30_fpu_calculate_wm_and_dlg()438 …r_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_ex… in dcn30_fpu_calculate_wm_and_dlg()439 ….soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; in dcn30_fpu_calculate_wm_and_dlg()507 …r_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_ex… in dcn30_fpu_calculate_wm_and_dlg()508 ….soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us; in dcn30_fpu_calculate_wm_and_dlg()587 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; in dcn30_fpu_calculate_wm_and_dlg()[all …]
199 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; in dcn32_build_wm_range_table_fpu()200 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_… in dcn32_build_wm_range_table_fpu()201 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn32_build_wm_range_table_fpu()202 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter… in dcn32_build_wm_range_table_fpu()211 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us; in dcn32_build_wm_range_table_fpu()212 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us = fclk_change_… in dcn32_build_wm_range_table_fpu()213 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn32_build_wm_range_table_fpu()214 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter… in dcn32_build_wm_range_table_fpu()224 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 50; in dcn32_build_wm_range_table_fpu()225 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us = fclk_change_… in dcn32_build_wm_range_table_fpu()[all …]
142 } dml_input; member
402 struct _vcs_dpi_display_e2e_pipe_params_st dml_input; member
464 struct _vcs_dpi_display_e2e_pipe_params_st *input = &pipe->dml_input; in dcn_bw_calc_rq_dlg_ttu()