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Searched refs:dmar_readq (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/iommu/intel/
H A Dsvm.c510 tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; in intel_drain_pasid_prq()
511 head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; in intel_drain_pasid_prq()
666 tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; in prq_event_thread()
667 head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; in prq_event_thread()
733 head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; in prq_event_thread()
734 tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; in prq_event_thread()
H A Ddebugfs.c145 value = dmar_readq(iommu->reg + iommu_regs_64[i].offset); in iommu_regset_show()
253 if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) { in ctx_tbl_walk()
444 dmar_readq(iommu->reg + DMAR_IQH_REG) >> shift, in invalidation_queue_show()
445 dmar_readq(iommu->reg + DMAR_IQT_REG) >> shift); in invalidation_queue_show()
H A Dperfmon.c329 new_count = dmar_readq(iommu_event_base(iommu_pmu, hwc->idx)); in iommu_pmu_event_update()
362 count = dmar_readq(iommu_event_base(iommu_pmu, hwc->idx)); in iommu_pmu_start()
518 while ((status = dmar_readq(iommu_pmu->overflow))) { in iommu_pmu_counter_overflow()
595 perfcap = dmar_readq(iommu->reg + DMAR_PERFCAP_REG); in alloc_iommu_pmu()
638 pcap = dmar_readq(iommu->reg + DMAR_PERFEVNTCAP_REG + in alloc_iommu_pmu()
H A Ddmar.c901 cap = dmar_readq(addr + DMAR_CAP_REG); in dmar_validate_one_drhd()
902 ecap = dmar_readq(addr + DMAR_ECAP_REG); in dmar_validate_one_drhd()
987 iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG); in map_iommu()
988 iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG); in map_iommu()
1022 iommu->ecmdcap[i] = dmar_readq(iommu->reg + DMAR_ECCAP_REG + in map_iommu()
1240 u64 iqe_err = dmar_readq(iommu->reg + DMAR_IQER_REG); in qi_dump_fault()
2052 guest_addr = dmar_readq(iommu->reg + reg + in dmar_fault()
H A Dpasid.c38 IOMMU_WAIT_OP(iommu, DMAR_VCRSP_REG, dmar_readq, in vcmd_alloc_pasid()
69 IOMMU_WAIT_OP(iommu, DMAR_VCRSP_REG, dmar_readq, in vcmd_free_pasid()
H A Diommu.c1301 dmar_readq, (!(val & DMA_CCMD_ICC)), val); in __iommu_flush_context()
1344 dmar_readq, (!(val & DMA_TLB_IVT)), val); in __iommu_flush_iotlb()
2694 rtaddr_reg = dmar_readq(iommu->reg + DMAR_RTADDR_REG); in copy_translation_tables()
5099 res = dmar_readq(iommu->reg + DMAR_ECRSP_REG); in ecmd_submit_sync()
5115 IOMMU_WAIT_OP(iommu, DMAR_ECRSP_REG, dmar_readq, in ecmd_submit_sync()
H A Diommu.h149 #define dmar_readq(a) readq(a) macro
H A Dirq_remapping.c430 irta = dmar_readq(iommu->reg + DMAR_IRTA_REG); in iommu_load_old_irte()