Searched refs:divider_ratio (Results 1 – 2 of 2) sorted by relevance
40 static u32 get_clk_reg_val(ulong divider_ratio) in get_clk_reg_val() argument45 for (div = 0; divider_ratio >= 16; div++) { in get_clk_reg_val()46 inc |= (divider_ratio & 1); in get_clk_reg_val()47 divider_ratio >>= 1; in get_clk_reg_val()49 divider_ratio += inc; in get_clk_reg_val()50 scl_low = (divider_ratio >> 1) - 1; in get_clk_reg_val()51 scl_high = divider_ratio - scl_low - 2; in get_clk_reg_val()
47 int divider_ratio; member85 .divider_ratio = AP806_PLL_CR_CPU_CLK_DIV_RATIO,119 .divider_ratio = AP807_PLL_CR_CPU_CLK_DIV_RATIO,181 if (clk->pll_regs->divider_ratio) { in ap_cpu_clk_set_rate()183 reg |= ((divider * clk->pll_regs->divider_ratio) << in ap_cpu_clk_set_rate()