Searched refs:div_peril0 (Results 1 – 5 of 5) sorted by relevance
72 writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0); in system_clock_init()
730 ratio = readl(&clk->div_peril0); in exynos4_get_uart_clk()775 ratio = readl(&clk->div_peril0); in exynos4x12_get_uart_clk()
98 unsigned int div_peril0; member335 unsigned int div_peril0; member
304 clrsetbits_le32(&clk->div_peril0, clr, set); in board_clock_init()
332 writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0); in board_clock_init()