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Searched refs:div_frc (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/clk/
H A Dclk-versaclock5.c173 u32 div_frc; member
435 u32 div_int, div_frc; in vc5_pll_recalc_rate() local
441 div_frc = (fb[2] << 16) | (fb[3] << 8) | fb[4]; in vc5_pll_recalc_rate()
444 return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24); in vc5_pll_recalc_rate()
453 u64 div_frc; in vc5_pll_round_rate() local
463 div_frc = rate % *parent_rate; in vc5_pll_round_rate()
464 div_frc *= BIT(24) - 1; in vc5_pll_round_rate()
465 do_div(div_frc, *parent_rate); in vc5_pll_round_rate()
468 hwdata->div_frc = (u32)div_frc; in vc5_pll_round_rate()
470 return (*parent_rate * div_int) + ((*parent_rate * div_frc) >> 24); in vc5_pll_round_rate()
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H A Dclk-versaclock3.c172 u32 div_frc; member
361 u32 div_int, div_frc, val; in vc3_pll_recalc_rate() local
371 div_frc = val << 8; in vc3_pll_recalc_rate()
373 div_frc |= val; in vc3_pll_recalc_rate()
375 (div_int * VC3_2_POW_16 + div_frc) / VC3_2_POW_16); in vc3_pll_recalc_rate()
388 u64 div_frc; in vc3_pll_round_rate() local
402 div_frc = rate % *parent_rate; in vc3_pll_round_rate()
403 div_frc *= BIT(16) - 1; in vc3_pll_round_rate()
405 vc3->div_frc = min_t(u64, div64_ul(div_frc, *parent_rate), U16_MAX); in vc3_pll_round_rate()
407 (vc3->div_int * VC3_2_POW_16 + vc3->div_frc) / VC3_2_POW_16); in vc3_pll_round_rate()
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