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Searched refs:div_disp1_0 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock.c987 ratio = readl(&clk->div_disp1_0); in exynos5_get_lcd_clk()
1164 clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0); in exynos5_set_lcd_clk()
H A Dclock_init_exynos5.c986 setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); in clock_init_dp_clock()
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dclock.h717 unsigned int div_disp1_0; member