| /openbmc/linux/drivers/clk/baikal-t1/ |
| H A D | ccu-div.c | 61 unsigned long div) in ccu_div_lock_delay_ns() argument
63 u64 ns = 4ULL * (div ?: 1) * NSEC_PER_SEC; in ccu_div_lock_delay_ns()
71 unsigned long div) in ccu_div_calc_freq() argument
73 return ref_clk / (div ?: 1); in ccu_div_calc_freq()
76 static int ccu_div_var_update_clkdiv(struct ccu_div *div, in ccu_div_var_update_clkdiv() argument
87 if (div->features & CCU_DIV_LOCK_SHIFTED) in ccu_div_var_update_clkdiv()
92 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_var_update_clkdiv()
102 regmap_read(div->sys_regs, div->reg_ctl, &val); in ccu_div_var_update_clkdiv()
113 struct ccu_div *div = to_ccu_div(hw); in ccu_div_var_enable() local
123 regmap_read(div->sys_regs, div->reg_ctl, &val); in ccu_div_var_enable()
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| /openbmc/linux/drivers/clk/berlin/ |
| H A D | berlin2-div.c | 67 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_is_enabled() local
68 struct berlin2_div_map *map = &div->map; in berlin2_div_is_enabled()
71 if (div->lock) in berlin2_div_is_enabled()
72 spin_lock(div->lock); in berlin2_div_is_enabled()
74 reg = readl_relaxed(div->base + map->gate_offs); in berlin2_div_is_enabled()
77 if (div->lock) in berlin2_div_is_enabled()
78 spin_unlock(div->lock); in berlin2_div_is_enabled()
85 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_enable() local
86 struct berlin2_div_map *map = &div->map; in berlin2_div_enable()
89 if (div->lock) in berlin2_div_enable()
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| /openbmc/linux/drivers/clk/ti/ |
| H A D | divider.c | 26 for (clkt = table; clkt->div; clkt++) in _get_table_div()
28 return clkt->div; in _get_table_div()
41 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
72 unsigned int div) in _get_table_val() argument
76 for (clkt = table; clkt->div; clkt++) in _get_table_val()
77 if (clkt->div == div) in _get_table_val()
82 static unsigned int _get_val(struct clk_omap_divider *divider, u8 div) in _get_val() argument
85 return div; in _get_val()
87 return __ffs(div); in _get_val()
89 return _get_table_val(divider->table, div); in _get_val()
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| /openbmc/linux/drivers/clk/imx/ |
| H A D | clk-divider-gate.c | 21 struct clk_divider *div = to_clk_divider(hw); in to_clk_divider_gate() local
23 return container_of(div, struct clk_divider_gate, divider); in to_clk_divider_gate()
29 struct clk_divider *div = to_clk_divider(hw); in clk_divider_gate_recalc_rate_ro() local
32 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate_ro()
33 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate_ro()
37 return divider_recalc_rate(hw, parent_rate, val, div->table, in clk_divider_gate_recalc_rate_ro()
38 div->flags, div->width); in clk_divider_gate_recalc_rate_ro()
45 struct clk_divider *div = to_clk_divider(hw); in clk_divider_gate_recalc_rate() local
49 spin_lock_irqsave(div->lock, flags); in clk_divider_gate_recalc_rate()
54 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate()
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| /openbmc/linux/drivers/clk/ |
| H A D | clk-divider.c | 51 for (clkt = table; clkt->div; clkt++) in _get_table_maxdiv()
52 if (clkt->div > maxdiv && clkt->val <= mask) in _get_table_maxdiv()
53 maxdiv = clkt->div; in _get_table_maxdiv()
62 for (clkt = table; clkt->div; clkt++) in _get_table_mindiv()
63 if (clkt->div < mindiv) in _get_table_mindiv()
64 mindiv = clkt->div; in _get_table_mindiv()
85 for (clkt = table; clkt->div; clkt++) in _get_table_div()
87 return clkt->div; in _get_table_div()
106 unsigned int div) in _get_table_val() argument
110 for (clkt = table; clkt->div; clkt++) in _get_table_val()
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| H A D | clk-fsl-flexspi.c | 14 { .val = 0, .div = 1, },
15 { .val = 1, .div = 2, },
16 { .val = 2, .div = 3, },
17 { .val = 3, .div = 4, },
18 { .val = 4, .div = 5, },
19 { .val = 5, .div = 6, },
20 { .val = 6, .div = 7, },
21 { .val = 7, .div = 8, },
22 { .val = 11, .div = 12, },
23 { .val = 15, .div = 16, },
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| H A D | clk-milbeaut.c | 83 u8 div; member
101 { .val = 0, .div = 8 },
102 { .val = 1, .div = 9 },
103 { .val = 2, .div = 10 },
104 { .val = 3, .div = 15 },
105 { .div = 0 },
109 { .val = 1, .div = 2 },
110 { .val = 3, .div = 4 },
111 { .div = 0 },
115 { .val = 3, .div = 4 },
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| H A D | clk-cdce706.c | 29 #define CDCE706_DIVIDER(div) (13 + (div)) argument
50 #define CDCE706_DIVIDER_PLL(div) (9 + (div) - ((div) > 2) - ((div) > 4)) argument
51 #define CDCE706_DIVIDER_PLL_SHIFT(div) ((div) < 2 ? 5 : 3 * ((div) & 1)) argument
52 #define CDCE706_DIVIDER_PLL_MASK(div) (0x7 << CDCE706_DIVIDER_PLL_SHIFT(div)) argument
72 unsigned div; member
170 __func__, hwd->idx, hwd->mux, hwd->mul, hwd->div); in cdce706_pll_recalc_rate()
173 if (hwd->div && hwd->mul) { in cdce706_pll_recalc_rate()
176 do_div(res, hwd->div); in cdce706_pll_recalc_rate()
180 if (hwd->div) in cdce706_pll_recalc_rate()
181 return parent_rate / hwd->div; in cdce706_pll_recalc_rate()
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| /openbmc/u-boot/arch/mips/mach-ath79/qca953x/ |
| H A D | clk.c | 34 u32 val, ctrl, xtal, pll, div; in get_clocks() local
44 div = (val >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) in get_clocks()
46 pll = xtal / div; in get_clocks()
49 div = (val >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) in get_clocks()
51 pll *= div; in get_clocks()
52 div = (val >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) in get_clocks()
54 if (!div) in get_clocks()
55 div = 1; in get_clocks()
56 pll >>= div; in get_clocks()
59 div = ((ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) in get_clocks()
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| /openbmc/linux/drivers/clk/mxs/ |
| H A D | clk-div.c | 38 struct clk_div *div = to_clk_div(hw); in clk_div_recalc_rate() local
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
46 struct clk_div *div = to_clk_div(hw); in clk_div_round_rate() local
48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
54 struct clk_div *div = to_clk_div(hw); in clk_div_set_rate() local
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
59 ret = mxs_clk_wait(div->reg, div->busy); in clk_div_set_rate()
73 struct clk_div *div; in mxs_clk_div() local
77 div = kzalloc(sizeof(*div), GFP_KERNEL); in mxs_clk_div()
78 if (!div) in mxs_clk_div()
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| /openbmc/linux/drivers/clk/sunxi/ |
| H A D | clk-sunxi.c | 35 u8 div; in sun4i_get_pll1_factors() local
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
52 if (div < 10) in sun4i_get_pll1_factors()
56 else if (div < 20 || (div < 32 && (div & 1))) in sun4i_get_pll1_factors()
61 else if (div < 40 || (div < 64 && (div & 2))) in sun4i_get_pll1_factors()
69 div <<= req->p; in sun4i_get_pll1_factors()
70 div /= (req->k + 1); in sun4i_get_pll1_factors()
71 req->n = div / 4; in sun4i_get_pll1_factors()
159 u8 div; in sun8i_a23_get_pll1_factors() local
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| H A D | clk-sun9i-cpus.c | 36 #define SUN9I_CPUS_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_DIV_MASK) | \ argument
37 (div << SUN9I_CPUS_DIV_SHIFT))
42 #define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) | \ argument
43 (div << SUN9I_CPUS_PLL4_DIV_SHIFT))
75 u8 div, pre_div = 1; in sun9i_a80_cpus_clk_round() local
84 div = DIV_ROUND_UP(parent_rate, rate); in sun9i_a80_cpus_clk_round()
87 if (parent == SUN9I_CPUS_MUX_PARENT_PLL4 && div > 4) { in sun9i_a80_cpus_clk_round()
89 if (div < 32) { in sun9i_a80_cpus_clk_round()
90 pre_div = div; in sun9i_a80_cpus_clk_round()
91 div = 1; in sun9i_a80_cpus_clk_round()
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| /openbmc/linux/drivers/clk/bcm/ |
| H A D | clk-iproc-asiu.c | 22 struct iproc_asiu_div div; member
82 val = readl(asiu->div_base + clk->div.offset); in iproc_asiu_clk_recalc_rate()
83 if ((val & (1 << clk->div.en_shift)) == 0) { in iproc_asiu_clk_recalc_rate()
89 div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width); in iproc_asiu_clk_recalc_rate()
91 div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width); in iproc_asiu_clk_recalc_rate()
104 unsigned int div; in iproc_asiu_clk_round_rate() local
112 div = DIV_ROUND_CLOSEST(*parent_rate, rate); in iproc_asiu_clk_round_rate()
113 if (div < 2) in iproc_asiu_clk_round_rate()
116 return *parent_rate / div; in iproc_asiu_clk_round_rate()
124 unsigned int div, div_h, div_l; in iproc_asiu_clk_set_rate() local
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| H A D | clk-kona.c | 50 static inline u64 scaled_div_value(struct bcm_clk_div *div, u32 reg_div) in scaled_div_value() argument
52 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value()
60 u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value, u32 billionths) in scaled_div_build() argument
68 combined <<= div->u.s.frac_width; in scaled_div_build()
75 scaled_div_min(struct bcm_clk_div *div) in scaled_div_min() argument
77 if (divider_is_fixed(div)) in scaled_div_min()
78 return (u64)div->u.fixed; in scaled_div_min()
80 return scaled_div_value(div, 0); in scaled_div_min()
84 u64 scaled_div_max(struct bcm_clk_div *div) in scaled_div_max() argument
88 if (divider_is_fixed(div)) in scaled_div_max()
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| /openbmc/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rv1108.c | 29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
66 const struct pll_div *div) in rkclk_set_pll() argument
72 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
73 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
76 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
77 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
93 rk_clrsetreg(&pll->con0, FBDIV_MASK, div->fbdiv << FBDIV_SHIFT); in rkclk_set_pll()
95 (div->postdiv1 << POSTDIV1_SHIFT | in rkclk_set_pll()
96 div->postdiv2 << POSTDIV2_SHIFT | in rkclk_set_pll()
97 div->refdiv << REFDIV_SHIFT)); in rkclk_set_pll()
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| /openbmc/linux/drivers/clk/meson/ |
| H A D | clk-regmap.c | 63 struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); in clk_regmap_div_recalc_rate() local
67 ret = regmap_read(clk->map, div->offset, &val); in clk_regmap_div_recalc_rate()
72 val >>= div->shift; in clk_regmap_div_recalc_rate()
73 val &= clk_div_mask(div->width); in clk_regmap_div_recalc_rate()
74 return divider_recalc_rate(hw, prate, val, div->table, div->flags, in clk_regmap_div_recalc_rate()
75 div->width); in clk_regmap_div_recalc_rate()
82 struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); in clk_regmap_div_determine_rate() local
87 if (div->flags & CLK_DIVIDER_READ_ONLY) { in clk_regmap_div_determine_rate()
88 ret = regmap_read(clk->map, div->offset, &val); in clk_regmap_div_determine_rate()
92 val >>= div->shift; in clk_regmap_div_determine_rate()
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| /openbmc/u-boot/arch/mips/mach-ath79/ar933x/ |
| H A D | clk.c | 34 u32 val, xtal, pll, div; in get_clocks() local
42 div = (val >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) in get_clocks()
44 pll = xtal / div; in get_clocks()
47 div = (val >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) in get_clocks()
49 pll *= div; in get_clocks()
50 div = (val >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) in get_clocks()
52 if (!div) in get_clocks()
53 div = 1; in get_clocks()
54 pll >>= div; in get_clocks()
59 div = ((val >> AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) in get_clocks()
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| /openbmc/linux/drivers/mmc/host/ |
| H A D | meson-mx-sdhc-clkc.c | 17 struct clk_divider div; member
32 { .div = 6, .val = 5, },
33 { .div = 8, .val = 7, },
34 { .div = 9, .val = 8, },
35 { .div = 10, .val = 9, },
36 { .div = 12, .val = 11, },
37 { .div = 16, .val = 15, },
38 { .div = 18, .val = 17, },
39 { .div = 34, .val = 33, },
40 { .div = 142, .val = 141, },
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| /openbmc/linux/drivers/clk/tegra/ |
| H A D | clk-divider.c | 24 int div; in get_div() local
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
29 if (div < 0) in get_div()
32 return div; in get_div()
40 int div, mul; in clk_frac_div_recalc_rate() local
49 div = (reg >> divider->shift) & div_mask(divider); in clk_frac_div_recalc_rate()
52 div += mul; in clk_frac_div_recalc_rate()
55 rate += div - 1; in clk_frac_div_recalc_rate()
56 do_div(rate, div); in clk_frac_div_recalc_rate()
65 int div, mul; in clk_frac_div_round_rate() local
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| /openbmc/linux/drivers/clk/ingenic/ |
| H A D | cgu.c | 412 u32 div_reg, div; in ingenic_clk_recalc_rate() local
418 if (!(clk_info->div.bypass_mask & BIT(parent))) { in ingenic_clk_recalc_rate()
419 div_reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_recalc_rate()
420 div = (div_reg >> clk_info->div.shift) & in ingenic_clk_recalc_rate()
421 GENMASK(clk_info->div.bits - 1, 0); in ingenic_clk_recalc_rate()
423 if (clk_info->div.div_table) in ingenic_clk_recalc_rate()
424 div = clk_info->div.div_table[div]; in ingenic_clk_recalc_rate()
426 div = (div + 1) * clk_info->div.div; in ingenic_clk_recalc_rate()
428 rate /= div; in ingenic_clk_recalc_rate()
431 rate /= clk_info->fixdiv.div; in ingenic_clk_recalc_rate()
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| /openbmc/u-boot/arch/arm/mach-s5pc1xx/ |
| H A D | clock.c | 137 unsigned long div; in s5pc110_get_arm_clk() local
141 div = readl(&clk->div0); in s5pc110_get_arm_clk()
144 apll_ratio = div & 0x7; in s5pc110_get_arm_clk()
157 unsigned long div; in s5pc100_get_arm_clk() local
161 div = readl(&clk->div0); in s5pc100_get_arm_clk()
164 arm_ratio = (div >> 4) & 0x7; in s5pc100_get_arm_clk()
166 apll_ratio = div & 0x1; in s5pc100_get_arm_clk()
180 uint div, d0_bus_ratio; in get_hclk() local
182 div = readl(&clk->div0); in get_hclk()
184 d0_bus_ratio = (div >> 8) & 0x7; in get_hclk()
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| /openbmc/linux/drivers/clk/spear/ |
| H A D | spear1340_clock.c | 188 {.div = 0x073A8}, /* for vco1div2 = 600 MHz */
189 {.div = 0x06062}, /* for vco1div2 = 500 MHz */
190 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
191 {.div = 0x04000}, /* for vco1div2 = 332 MHz */
192 {.div = 0x03031}, /* for vco1div2 = 250 MHz */
193 {.div = 0x0268D}, /* for vco1div2 = 200 MHz */
240 {.div = 0x08000},
241 {.div = 0x06a38},
242 {.div = 0x06666},
243 {.div = 0x06000},
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| /openbmc/linux/drivers/clk/zynqmp/ |
| H A D | divider.c | 86 u32 div, value; in zynqmp_clk_divider_recalc_rate() local
89 ret = zynqmp_pm_clock_getdivider(clk_id, &div); in zynqmp_clk_divider_recalc_rate()
96 value = div & 0xFFFF; in zynqmp_clk_divider_recalc_rate()
98 value = div >> 16; in zynqmp_clk_divider_recalc_rate()
176 u32 value, div; in zynqmp_clk_divider_set_rate() local
181 div = value & 0xFFFF; in zynqmp_clk_divider_set_rate()
182 div |= 0xffff << 16; in zynqmp_clk_divider_set_rate()
184 div = 0xffff; in zynqmp_clk_divider_set_rate()
185 div |= value << 16; in zynqmp_clk_divider_set_rate()
189 div = __ffs(div); in zynqmp_clk_divider_set_rate()
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| /openbmc/linux/drivers/media/platform/st/sti/hva/ |
| H A D | hva-debugfs.c | 121 u64 div; in hva_dbg_perf_begin() local
131 div = (u64)ktime_us_delta(dbg->begin, prev); in hva_dbg_perf_begin()
132 do_div(div, 100); in hva_dbg_perf_begin()
133 period = (u32)div; in hva_dbg_perf_begin()
152 div = (u64)dbg->window_stream_size * 80; in hva_dbg_perf_begin()
153 do_div(div, dbg->window_duration); in hva_dbg_perf_begin()
154 bitrate = (u32)div; in hva_dbg_perf_begin()
178 u64 div; in hva_dbg_perf_end() local
187 div = stream->vbuf.vb2_buf.timestamp; in hva_dbg_perf_end()
188 do_div(div, 1000); in hva_dbg_perf_end()
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| /openbmc/linux/drivers/clk/x86/ |
| H A D | clk-cgu.c | 165 struct lgm_clk_divider *div = to_lgm_clk_divider(hw); in lgm_clk_divider_enable_disable() local
167 if (div->flags != DIV_CLK_NO_MASK) in lgm_clk_divider_enable_disable()
168 lgm_set_clk_val(div->membase, div->reg, div->shift_gate, in lgm_clk_divider_enable_disable()
169 div->width_gate, enable); in lgm_clk_divider_enable_disable()
197 struct lgm_clk_divider *div; in lgm_clk_register_divider() local
207 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); in lgm_clk_register_divider()
208 if (!div) in lgm_clk_register_divider()
217 div->membase = ctx->membase; in lgm_clk_register_divider()
218 div->reg = reg; in lgm_clk_register_divider()
219 div->shift = shift; in lgm_clk_register_divider()
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