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Searched refs:display_config (Results 1 – 22 of 22) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dhardwaremanager.c305 const struct amd_pp_display_configuration *display_config) in phm_store_dal_configuration_data() argument
312 if (display_config == NULL) in phm_store_dal_configuration_data()
316 hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, display_config->min_dcef_deep_sleep_set_clk); in phm_store_dal_configuration_data()
318 for (index = 0; index < display_config->num_path_including_non_display; index++) { in phm_store_dal_configuration_data()
319 if (display_config->displays[index].controller_id != 0) in phm_store_dal_configuration_data()
333 display_config->cpu_pstate_separation_time, in phm_store_dal_configuration_data()
334 display_config->cpu_cc6_disable, in phm_store_dal_configuration_data()
335 display_config->cpu_pstate_disable, in phm_store_dal_configuration_data()
336 display_config->nb_pstate_switch_disable); in phm_store_dal_configuration_data()
H A Dvega12_hwmgr.c1623 if ((hwmgr->display_config->num_display > 1) && in vega12_notify_smc_display_config_after_ps_adjustment()
1624 !hwmgr->display_config->multi_monitor_in_sync && in vega12_notify_smc_display_config_after_ps_adjustment()
1625 !hwmgr->display_config->nb_pstate_switch_disable) in vega12_notify_smc_display_config_after_ps_adjustment()
1630 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1631 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1632 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega12_notify_smc_display_config_after_ps_adjustment()
2366 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega12_apply_clocks_adjust_rules()
2367 !hwmgr->display_config->multi_monitor_in_sync) || in vega12_apply_clocks_adjust_rules()
2369 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega12_apply_clocks_adjust_rules()
2420 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) in vega12_apply_clocks_adjust_rules()
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H A Dvega20_hwmgr.c2358 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()
2359 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()
2360 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega20_notify_smc_display_config_after_ps_adjustment()
3673 hwmgr->display_config->num_display, in vega20_display_configuration_changed_task()
3748 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega20_apply_clocks_adjust_rules()
3749 !hwmgr->display_config->multi_monitor_in_sync) || in vega20_apply_clocks_adjust_rules()
3751 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega20_apply_clocks_adjust_rules()
3802 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) in vega20_apply_clocks_adjust_rules()
3803 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100; in vega20_apply_clocks_adjust_rules()
3810 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) { in vega20_apply_clocks_adjust_rules()
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H A Dsmu10_hwmgr.c194 clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in smu10_set_clock_limit()
628 uint32_t min_sclk = hwmgr->display_config->min_core_set_clock; in smu10_dpm_force_dpm_level()
629 uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100; in smu10_dpm_force_dpm_level()
785 hwmgr->display_config->num_display > 3 ? in smu10_dpm_force_dpm_level()
H A Dvega10_hwmgr.c3328 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in vega10_apply_state_adjust_rules()
3329 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega10_apply_state_adjust_rules()
3369 if (hwmgr->display_config->num_display == 0) in vega10_apply_state_adjust_rules()
3372 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega10_apply_state_adjust_rules()
3373 !hwmgr->display_config->multi_monitor_in_sync) || in vega10_apply_state_adjust_rules()
3405 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega10_apply_state_adjust_rules()
3475 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) in vega10_find_dpm_states_clocks_in_dpm_table()
4105 if ((hwmgr->display_config->num_display > 1) && in vega10_notify_smc_display_config_after_ps_adjustment()
4106 !hwmgr->display_config->multi_monitor_in_sync && in vega10_notify_smc_display_config_after_ps_adjustment()
4107 !hwmgr->display_config->nb_pstate_switch_disable) in vega10_notify_smc_display_config_after_ps_adjustment()
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H A Dsmu7_hwmgr.c3356 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in smu7_apply_state_adjust_rules()
3357 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in smu7_apply_state_adjust_rules()
3387 disable_mclk_switching_for_display = ((1 < hwmgr->display_config->num_display) && in smu7_apply_state_adjust_rules()
3388 !hwmgr->display_config->multi_monitor_in_sync) || in smu7_apply_state_adjust_rules()
3389 (hwmgr->display_config->num_display && in smu7_apply_state_adjust_rules()
3390 smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time)); in smu7_apply_state_adjust_rules()
3395 if (hwmgr->display_config->num_display == 0) { in smu7_apply_state_adjust_rules()
3437 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in smu7_apply_state_adjust_rules()
4126 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) in smu7_find_dpm_states_clocks_in_dpm_table()
4583 …display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->nu… in smu7_program_display_gap()
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H A Dsmu8_hwmgr.c711 clock = hwmgr->display_config->min_core_set_clock; in smu8_update_sclk_limit()
769 uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr; in smu8_set_deep_sleep_sclk_threshold()
1093 clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ? in smu8_apply_state_adjust_rules()
1094 hwmgr->display_config->min_mem_set_clock : in smu8_apply_state_adjust_rules()
1102 || (hwmgr->display_config->num_display >= 3); in smu8_apply_state_adjust_rules()
/openbmc/linux/arch/arm/mach-davinci/
H A Dda8xx.h76 (struct vpif_display_config *display_config);
H A Dda850.c333 *display_config) in da850_register_vpif_display()
335 da850_vpif_display_dev.dev.platform_data = display_config; in da850_register_vpif_display()
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dhardwaremanager.h428 const struct amd_pp_display_configuration *display_config);
H A Dhwmgr.h794 const struct amd_pp_display_configuration *display_config; member
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/
H A Damd_powerplay.c58 hwmgr->display_config = &adev->pm.pm_display_cfg; in amd_powerplay_create()
1034 const struct amd_pp_display_configuration *display_config) in pp_display_configuration_change() argument
1041 phm_store_dal_configuration_data(hwmgr, display_config); in pp_display_configuration_change()
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvegam_smumgr.c839 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in vegam_populate_single_graphic_level()
843 hwmgr->display_config->min_core_set_clock_in_sr); in vegam_populate_single_graphic_level()
1013 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in vegam_populate_single_memory_level()
1014 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in vegam_populate_single_memory_level()
H A Dfiji_smumgr.c974 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in fiji_populate_single_graphic_level()
978 hwmgr->display_config->min_core_set_clock_in_sr); in fiji_populate_single_graphic_level()
1199 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in fiji_populate_single_memory_level()
1200 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in fiji_populate_single_memory_level()
H A Dpolaris10_smumgr.c993 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in polaris10_populate_single_graphic_level()
997 hwmgr->display_config->min_core_set_clock_in_sr); in polaris10_populate_single_graphic_level()
1188 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in polaris10_populate_single_memory_level()
1189 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in polaris10_populate_single_memory_level()
H A Diceland_smumgr.c932 hwmgr->display_config->min_core_set_clock_in_sr; in iceland_populate_single_graphic_level()
1282 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in iceland_populate_single_memory_level()
1283 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in iceland_populate_single_memory_level()
H A Dtonga_smumgr.c659 hwmgr->display_config->min_core_set_clock_in_sr; in tonga_populate_single_graphic_level()
1016 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in tonga_populate_single_memory_level()
1017 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in tonga_populate_single_memory_level()
H A Dci_smumgr.c1236 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in ci_populate_single_memory_level()
1237 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in ci_populate_single_memory_level()
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/
H A Damdgpu_smu.c1141 smu->display_config = &adev->pm.pm_display_cfg; in smu_sw_init()
1766 const struct amd_pp_display_configuration *display_config) in smu_display_configuration_change() argument
1773 if (!display_config) in smu_display_configuration_change()
1777 display_config->min_dcef_deep_sleep_set_clk / 100); in smu_display_configuration_change()
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/inc/
H A Damdgpu_smu.h488 struct amd_pp_display_configuration *display_config; member
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dnavi10_ppt.c1870 smu->display_config->num_display, in navi10_display_config_changed()
2099 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; in navi10_notify_smc_display_config()
2100 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; in navi10_notify_smc_display_config()
2101 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in navi10_notify_smc_display_config()
H A Dsienna_cichlid_ppt.c1555 smu->display_config->num_display, in sienna_cichlid_display_config_changed()
1784 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; in sienna_cichlid_notify_smc_display_config()
1785 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; in sienna_cichlid_notify_smc_display_config()
1786 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in sienna_cichlid_notify_smc_display_config()