Searched refs:ddr_timing (Results 1 – 3 of 3) sorted by relevance
| /openbmc/u-boot/arch/arm/mach-rockchip/rk3036/ |
| H A D | sdram_rk3036.c | 43 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
401 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
461 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
466 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
471 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
476 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
603 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
608 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
629 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
635 clrsetbits_le32(&ddr_phy->ddrphy_reg3, 1, ddr_timing.phy_timing.bl); in phy_cfg()
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| /openbmc/linux/drivers/mmc/host/ |
| H A D | dw_mmc-exynos.c | 39 u32 ddr_timing; member
325 clksel = priv->ddr_timing; in dw_mci_exynos_set_ios()
336 clksel = (priv->ddr_timing & 0xfff8ffff) | in dw_mci_exynos_set_ios()
392 priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); in dw_mci_exynos_parse_dt()
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| /openbmc/u-boot/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.c | 74 static const struct reg_desc ddr_timing[] = { variable
198 "timing", ddr_timing, ARRAY_SIZE(ddr_timing), DDR_BASE},
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