Searched refs:ddr_reg (Results 1 – 12 of 12) sorted by relevance
/openbmc/linux/drivers/perf/amlogic/ |
H A D | meson_g12_ddr_pmu.c | 179 r = readl(db->ddr_reg[0] + (DMC_MON_G12_CTRL0 + (i << 2))); in g12_dump_reg() 182 r = readl(db->ddr_reg[0] + DMC_MON_G12_ALL_REQ_CNT); in g12_dump_reg() 184 r = readl(db->ddr_reg[0] + DMC_MON_G12_ALL_GRANT_CNT); in g12_dump_reg() 186 r = readl(db->ddr_reg[0] + DMC_MON_G12_ONE_GRANT_CNT); in g12_dump_reg() 188 r = readl(db->ddr_reg[0] + DMC_MON_G12_SEC_GRANT_CNT); in g12_dump_reg() 190 r = readl(db->ddr_reg[0] + DMC_MON_G12_THD_GRANT_CNT); in g12_dump_reg() 192 r = readl(db->ddr_reg[0] + DMC_MON_G12_FOR_GRANT_CNT); in g12_dump_reg() 194 r = readl(db->ddr_reg[0] + DMC_MON_G12_TIMER); in g12_dump_reg() 204 writel(clock_count, info->ddr_reg[0] + DMC_MON_G12_TIMER); in dmc_g12_counter_enable() 206 val = readl(info->ddr_reg[0] + DMC_MON_G12_CTRL0); in dmc_g12_counter_enable() [all …]
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H A D | meson_ddr_pmu_core.c | 457 info->ddr_reg[i] = base; in ddr_pmu_parse_dt()
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/openbmc/linux/arch/mips/rb532/ |
H A D | prom.c | 27 static struct resource ddr_reg[] = { variable 107 ddr = ioremap(ddr_reg[0].start, in prom_init() 108 ddr_reg[0].end - ddr_reg[0].start); in prom_init()
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/openbmc/u-boot/drivers/ddr/fsl/ |
H A D | main.c | 426 fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg; in fsl_ddr_compute() local 567 memset(&ddr_reg[i], 0, in fsl_ddr_compute() 575 &ddr_reg[i], &timing_params[i], in fsl_ddr_compute() 596 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i]; in fsl_ddr_compute()
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/openbmc/linux/include/soc/amlogic/ |
H A D | meson_ddr_pmu.h | 57 void __iomem *ddr_reg[4]; member
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/openbmc/u-boot/drivers/ram/stm32mp1/ |
H A D | stm32mp1_ddr.c | 45 static const struct reg_desc ddr_reg[] = { variable 196 "static", ddr_reg, ARRAY_SIZE(ddr_reg), DDR_BASE},
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/openbmc/linux/arch/arm/boot/dts/nvidia/ |
H A D | tegra30-cardhu-a02.dts | 19 ddr_reg: regulator-ddr { label
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H A D | tegra30-cardhu-a04.dts | 19 ddr_reg: regulator-ddr { label
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H A D | tegra30-beaver.dts | 2033 ddr_reg: regulator-ddr { label
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H A D | tegra30-ouya.dts | 4703 ddr_reg: regulator-ddr { label
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/openbmc/u-boot/arch/arm/dts/ |
H A D | tegra30-beaver.dts | 258 ddr_reg: regulator@2 { label
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H A D | tegra30-cardhu.dts | 371 ddr_reg: regulator@100 { label
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