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Searched refs:ddr_pll (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/arch/mips/ath79/
H A Dclock.c239 u32 cpu_pll, ddr_pll; in ar934x_clocks_init() local
304 ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint, in ar934x_clocks_init()
317 cpu_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
325 ddr_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
335 ahb_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
357 u32 cpu_pll, ddr_pll; in qca953x_clocks_init() local
392 ddr_pll = nint * ref_rate / ref_div; in qca953x_clocks_init()
393 ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4); in qca953x_clocks_init()
394 ddr_pll /= (1 << out_div); in qca953x_clocks_init()
406 cpu_rate = ddr_pll / (postdiv + 1); in qca953x_clocks_init()
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/openbmc/u-boot/arch/mips/mach-ath79/ar934x/
H A Dclk.c43 struct ar934x_pll_config ddr_pll; member
111 u32 reg, cpu_pll, cpu_srif, ddr_pll, ddr_srif; in ar934x_pll_init() local
151 pll_cfg = &ar934x_clock_config[i].ddr_pll; in ar934x_pll_init()
154 ddr_pll = in ar934x_pll_init()
178 writel(ddr_pll | AR934X_PLL_DDR_CONFIG_PLLPWD, in ar934x_pll_init()
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Damlogic,meson8b-clkc.txt17 * "ddr_pll": the DDR PLL clock
/openbmc/qemu/hw/misc/
H A Dzynq_slcr.c280 uint64_t ddr_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_CTRL]); in zynq_slcr_compute_clocks_internal() local
282 uint64_t uart_mux[4] = {io_pll, io_pll, arm_pll, ddr_pll}; in zynq_slcr_compute_clocks_internal()
/openbmc/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8.dtsi631 clock-names = "xtal", "ddr_pll";
H A Dmeson8b.dtsi592 clock-names = "xtal", "ddr_pll";