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Searched refs:ddr_out32 (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/drivers/ddr/fsl/
H A Dfsl_ddr_gen4.c26 ddr_out32(ptr, value); in set_wait_for_bits_clear()
102 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); in fsl_ddr_set_memctl_regs()
105 ddr_out32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
107 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); in fsl_ddr_set_memctl_regs()
112 ddr_out32(&ddr->cs0_bnds, in fsl_ddr_set_memctl_regs()
114 ddr_out32(&ddr->cs0_config, in fsl_ddr_set_memctl_regs()
118 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
119 ddr_out32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
121 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
125 ddr_out32(&ddr->cs1_bnds, in fsl_ddr_set_memctl_regs()
[all …]
H A Darm_ddr_gen3.c67 ddr_out32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
70 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
71 ddr_out32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
72 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
75 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
76 ddr_out32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
77 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
80 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
81 ddr_out32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
82 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
[all …]
H A Dutil.c386 ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]); in fsl_ddr_sync_memctl_refresh()
/openbmc/linux/drivers/edac/
H A Dfsl_ddr_edac.c43 static inline void ddr_out32(void __iomem *addr, u32 value) in ddr_out32() function
100 ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI, val); in fsl_mc_inject_data_hi_store()
120 ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO, val); in fsl_mc_inject_data_lo_store()
140 ddr_out32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT, val); in fsl_mc_inject_ctrl_store()
298 ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect); in fsl_mc_check()
374 ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect); in fsl_mc_check()
566 ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE, 0); in fsl_mc_err_probe()
569 ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, ~0); in fsl_mc_err_probe()
578 ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN, in fsl_mc_err_probe()
586 ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, 0x10000); in fsl_mc_err_probe()
[all …]
/openbmc/u-boot/include/
H A Dfsl_ddr.h22 #define ddr_out32(a, v) out_le32(a, v) macro
28 #define ddr_out32(a, v) out_be32(a, v) macro
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dsoc.c425 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); in erratum_a008850_early()
448 ddr_out32(&ddr->eor, tmp); in erratum_a008850_post()
540 ddr_out32(&ddr->ddr_cdr1, tmp); in ddr_enable_0v9_volt()