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Searched refs:ddr_clk_ctrl (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-zynq/include/mach/
H A Dhardware.h40 u32 ddr_clk_ctrl; /* 0x124 */ member
/openbmc/u-boot/drivers/clk/
H A Dclk_zynq.c205 clk_ctrl = readl(&slcr_base->ddr_clk_ctrl); in zynq_clk_get_ddr2x_rate()
217 clk_ctrl = readl(&slcr_base->ddr_clk_ctrl); in zynq_clk_get_ddr3x_rate()