| /openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | dccg.h | 66 struct dccg { struct
88 void (*update_dpp_dto)(struct dccg *dccg, argument
91 void (*get_dccg_ref_freq)(struct dccg *dccg,
94 void (*set_fifo_errdet_ovr_en)(struct dccg *dccg,
96 void (*otg_add_pixel)(struct dccg *dccg,
98 void (*otg_drop_pixel)(struct dccg *dccg,
100 void (*dccg_init)(struct dccg *dccg);
103 struct dccg *dccg,
109 struct dccg *dccg,
114 struct dccg *dccg,
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| H A D | dcn31_dccg.c | 31 #define TO_DCN_DCCG(dccg)\ argument
32 container_of(dccg, struct dcn_dccg, base)
44 dccg->ctx->logger
46 void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg31_update_dpp_dto() argument
48 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg31_update_dpp_dto()
50 if (dccg->dpp_clock_gated[dpp_inst]) { in dccg31_update_dpp_dto()
58 if (dccg->ref_dppclk && req_dppclk) { in dccg31_update_dpp_dto()
59 int ref_dppclk = dccg->ref_dppclk; in dccg31_update_dpp_dto()
80 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg31_update_dpp_dto()
97 static void dccg31_enable_dpstreamclk(struct dccg *dccg, int otg_inst) in dccg31_enable_dpstreamclk() argument
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| H A D | dcn31_dccg.h | 156 struct dccg *dccg31_create(
162 void dccg31_init(struct dccg *dccg);
165 struct dccg *dccg,
170 struct dccg *dccg,
174 struct dccg *dccg,
179 struct dccg *dccg,
183 struct dccg *dccg,
188 struct dccg *dccg,
194 struct dccg *dccg,
198 struct dccg *dccg,
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| H A D | dcn31_hwseq.c | 126 if (res_pool->dccg->funcs->dccg_init) in dcn31_init_hw()
127 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn31_init_hw()
135 if (res_pool->dccg && res_pool->hubbub) { in dcn31_init_hw()
137 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn31_init_hw()
290 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && in dcn31_dsc_pg_control()
292 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( in dcn31_dsc_pg_control()
293 hws->ctx->dc->res_pool->dccg, dsc_inst); in dcn31_dsc_pg_control()
333 if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) in dcn31_dsc_pg_control()
334 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( in dcn31_dsc_pg_control()
335 hws->ctx->dc->res_pool->dccg, dsc_inst); in dcn31_dsc_pg_control()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_dccg.c | 32 #define TO_DCN_DCCG(dccg)\ argument
33 container_of(dccg, struct dcn_dccg, base)
45 dccg->ctx->logger
47 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg2_update_dpp_dto() argument
49 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_update_dpp_dto()
51 if (dccg->ref_dppclk && req_dppclk) { in dccg2_update_dpp_dto()
52 int ref_dppclk = dccg->ref_dppclk; in dccg2_update_dpp_dto()
74 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg2_update_dpp_dto()
77 void dccg2_get_dccg_ref_freq(struct dccg *dccg, in dccg2_get_dccg_ref_freq() argument
81 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_get_dccg_ref_freq()
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| H A D | dcn20_dccg.h | 298 struct dccg base;
304 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
306 void dccg2_get_dccg_ref_freq(struct dccg *dccg,
310 void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,
312 void dccg2_otg_add_pixel(struct dccg *dccg,
314 void dccg2_otg_drop_pixel(struct dccg *dccg,
318 void dccg2_init(struct dccg *dccg);
320 struct dccg *dccg2_create(
326 void dcn_dccg_destroy(struct dccg **dccg);
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/ |
| H A D | dcn314_dccg.c | 33 #define TO_DCN_DCCG(dccg)\ argument
34 container_of(dccg, struct dcn_dccg, base)
46 dccg->ctx->logger
49 struct dccg *dccg) in dccg314_trigger_dio_fifo_resync() argument
51 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_trigger_dio_fifo_resync()
59 struct dccg *dccg, in dccg314_get_pixel_rate_div() argument
64 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_get_pixel_rate_div()
101 struct dccg *dccg, in dccg314_set_pixel_rate_div() argument
106 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_set_pixel_rate_div()
116 dccg314_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2); in dccg314_set_pixel_rate_div()
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| H A D | dcn314_hwseq.c | 250 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && in dcn314_dsc_pg_control()
252 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( in dcn314_dsc_pg_control()
253 hws->ctx->dc->res_pool->dccg, dsc_inst); in dcn314_dsc_pg_control()
301 if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) in dcn314_dsc_pg_control()
302 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( in dcn314_dsc_pg_control()
303 hws->ctx->dc->res_pool->dccg, dsc_inst); in dcn314_dsc_pg_control()
412 hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg); in dcn314_resync_fifo_dccg_dio()
427 if (hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control) in dcn314_dpp_root_clock_control()
428 hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control( in dcn314_dpp_root_clock_control()
429 hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on); in dcn314_dpp_root_clock_control()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
46 struct dccg *dccg) in dccg32_trigger_dio_fifo_resync() argument
48 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_trigger_dio_fifo_resync()
59 struct dccg *dccg, in dccg32_get_pixel_rate_div() argument
64 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_get_pixel_rate_div()
101 struct dccg *dccg, in dccg32_set_pixel_rate_div() argument
106 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_set_pixel_rate_div()
117 dccg32_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2); in dccg32_set_pixel_rate_div()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
| H A D | dcn21_dccg.c | 31 #define TO_DCN_DCCG(dccg)\ argument
32 container_of(dccg, struct dcn_dccg, base)
44 dccg->ctx->logger
46 static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg21_update_dpp_dto() argument
48 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg21_update_dpp_dto()
50 if (dccg->ref_dppclk) { in dccg21_update_dpp_dto()
51 int ref_dppclk = dccg->ref_dppclk; in dccg21_update_dpp_dto()
96 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg21_update_dpp_dto()
109 struct dccg *dccg21_create( in dccg21_create()
116 struct dccg *base; in dccg21_create()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_dccg.c | 31 #define TO_DCN_DCCG(dccg)\ argument
32 container_of(dccg, struct dcn_dccg, base)
45 dccg->ctx->logger
47 static void dccg201_update_dpp_dto(struct dccg *dccg, int dpp_inst, in dccg201_update_dpp_dto() argument
62 struct dccg *dccg201_create( in dccg201_create()
69 struct dccg *base; in dccg201_create()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 109 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
119 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; in dcn20_update_clocks_update_dpp_dto()
122 clk_mgr->dccg->funcs->update_dpp_dto( in dcn20_update_clocks_update_dpp_dto()
123 clk_mgr->dccg, dpp_inst, dppclk_khz); in dcn20_update_clocks_update_dpp_dto()
155 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist() local
168 dccg->funcs->set_fifo_errdet_ovr_en( in dcn20_update_clocks_update_dentist()
169 dccg, in dcn20_update_clocks_update_dentist()
172 dccg->funcs->otg_drop_pixel( in dcn20_update_clocks_update_dentist()
173 dccg, in dcn20_update_clocks_update_dentist()
175 dccg->funcs->set_fifo_errdet_ovr_en( in dcn20_update_clocks_update_dentist()
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| H A D | dcn20_clk_mgr.h | 29 void dcn2_update_clocks(struct clk_mgr *dccg,
44 struct dccg *dccg);
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
55 struct dccg *dccg3_create( in dccg3_create()
62 struct dccg *base; in dccg3_create()
80 struct dccg *dccg30_create( in dccg30_create()
87 struct dccg *base; in dccg30_create()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/ |
| H A D | clk_mgr.c | 151 … clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg) in dc_clk_mgr_create() argument
237 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
242 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
264 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
268 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
272 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
276 dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
279 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
290 vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
303 dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn301/ |
| H A D | dcn301_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
54 struct dccg *dccg301_create( in dccg301_create()
61 struct dccg *base; in dccg301_create()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 249 struct dccg *dccg = clk_mgr->dccg; in dcn32_update_clocks_update_dtb_dto() local
265 dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params); in dcn32_update_clocks_update_dtb_dto()
298 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn32_update_clocks_update_dpp_dto()
319 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; in dcn32_update_clocks_update_dpp_dto()
322 clk_mgr->dccg->funcs->update_dpp_dto( in dcn32_update_clocks_update_dpp_dto()
323 clk_mgr->dccg, dpp_inst, dppclk_khz); in dcn32_update_clocks_update_dpp_dto()
353 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn32_update_clocks_update_dentist() local
366 dccg->funcs->set_fifo_errdet_ovr_en( in dcn32_update_clocks_update_dentist()
367 dccg, in dcn32_update_clocks_update_dentist()
370 dccg->funcs->otg_drop_pixel( in dcn32_update_clocks_update_dentist()
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| H A D | dcn32_clk_mgr.h | 33 struct dccg *dccg);
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/link/hwss/ |
| H A D | link_hwss_hpo_dp.c | 118 if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) in enable_hpo_dp_link_output()
119 link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( in enable_hpo_dp_link_output()
120 link->dc->res_pool->dccg, in enable_hpo_dp_link_output()
142 if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) in disable_hpo_dp_link_output()
143 link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( in disable_hpo_dp_link_output()
144 link->dc->res_pool->dccg, in disable_hpo_dp_link_output()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.h | 32 struct dccg *dccg);
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_clk_mgr.h | 45 struct dccg *dccg);
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_clk_mgr.h | 45 struct dccg *dccg);
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.h | 47 struct dccg *dccg);
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.h | 48 struct dccg *dccg);
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_clk_mgr.h | 53 struct dccg *dccg);
|