| /openbmc/u-boot/board/freescale/common/ |
| H A D | ics307_clk.c | 100 static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2) in ics307_clk_freq() argument
103 unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); in ics307_clk_freq()
126 debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2, in ics307_clk_freq()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dmub/src/ |
| H A D | dmub_dcn32.c | 148 const struct dmub_window *cw1) in dmub_dcn32_backdoor_load() argument
166 dmub_dcn32_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); in dmub_dcn32_backdoor_load()
170 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); in dmub_dcn32_backdoor_load()
172 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, in dmub_dcn32_backdoor_load()
181 const struct dmub_window *cw1) in dmub_dcn32_backdoor_load_zfb_mode() argument
196 offset = cw1->offset; in dmub_dcn32_backdoor_load_zfb_mode()
200 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); in dmub_dcn32_backdoor_load_zfb_mode()
202 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, in dmub_dcn32_backdoor_load_zfb_mode()
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| H A D | dmub_dcn30.c | 89 const struct dmub_window *cw1) in dmub_dcn30_backdoor_load() argument
109 dmub_dcn30_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); in dmub_dcn30_backdoor_load()
113 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); in dmub_dcn30_backdoor_load()
115 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, in dmub_dcn30_backdoor_load()
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| H A D | dmub_dcn20.c | 156 const struct dmub_window *cw1) in dmub_dcn20_backdoor_load() argument
176 dmub_dcn20_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); in dmub_dcn20_backdoor_load()
180 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); in dmub_dcn20_backdoor_load()
182 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, in dmub_dcn20_backdoor_load()
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| H A D | dmub_dcn30.h | 39 const struct dmub_window *cw1);
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| H A D | dmub_dcn31.c | 154 const struct dmub_window *cw1) in dmub_dcn31_backdoor_load() argument
172 dmub_dcn31_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); in dmub_dcn31_backdoor_load()
176 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); in dmub_dcn31_backdoor_load()
178 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, in dmub_dcn31_backdoor_load()
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| H A D | dmub_srv.c | 540 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; in dmub_srv_hw_init() local
566 cw1.offset.quad_part = stack_fb->gpu_addr; in dmub_srv_hw_init()
567 cw1.region.base = DMUB_CW1_BASE; in dmub_srv_hw_init()
568 cw1.region.top = cw1.region.base + stack_fb->size - 1; in dmub_srv_hw_init()
582 dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1); in dmub_srv_hw_init()
584 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); in dmub_srv_hw_init()
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| H A D | dmub_dcn32.h | 194 const struct dmub_window *cw1);
198 const struct dmub_window *cw1);
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| H A D | dmub_dcn20.h | 193 const struct dmub_window *cw1);
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| H A D | dmub_dcn31.h | 195 const struct dmub_window *cw1);
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| /openbmc/linux/drivers/gpu/drm/amd/display/dmub/ |
| H A D | dmub_srv.h | 335 const struct dmub_window *cw1);
339 const struct dmub_window *cw1);
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