| /openbmc/u-boot/board/freescale/common/ |
| H A D | ics307_clk.c | 100 static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2) in ics307_clk_freq() argument
105 unsigned long od = ics307_s_to_od[cw0 & 0x7]; in ics307_clk_freq()
126 debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2, in ics307_clk_freq()
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dmub/src/ |
| H A D | dmub_dcn32.c | 147 const struct dmub_window *cw0, in dmub_dcn32_backdoor_load() argument
157 dmub_dcn32_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); in dmub_dcn32_backdoor_load()
161 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); in dmub_dcn32_backdoor_load()
163 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, in dmub_dcn32_backdoor_load()
180 const struct dmub_window *cw0, in dmub_dcn32_backdoor_load_zfb_mode() argument
187 offset = cw0->offset; in dmub_dcn32_backdoor_load_zfb_mode()
191 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); in dmub_dcn32_backdoor_load_zfb_mode()
193 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, in dmub_dcn32_backdoor_load_zfb_mode()
|
| H A D | dmub_dcn30.c | 88 const struct dmub_window *cw0, in dmub_dcn30_backdoor_load() argument
100 dmub_dcn30_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); in dmub_dcn30_backdoor_load()
104 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); in dmub_dcn30_backdoor_load()
106 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, in dmub_dcn30_backdoor_load()
|
| H A D | dmub_dcn20.c | 155 const struct dmub_window *cw0, in dmub_dcn20_backdoor_load() argument
167 dmub_dcn20_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); in dmub_dcn20_backdoor_load()
171 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); in dmub_dcn20_backdoor_load()
173 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, in dmub_dcn20_backdoor_load()
|
| H A D | dmub_dcn30.h | 38 const struct dmub_window *cw0,
|
| H A D | dmub_dcn31.c | 153 const struct dmub_window *cw0, in dmub_dcn31_backdoor_load() argument
163 dmub_dcn31_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); in dmub_dcn31_backdoor_load()
167 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); in dmub_dcn31_backdoor_load()
169 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, in dmub_dcn31_backdoor_load()
|
| H A D | dmub_srv.c | 540 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; in dmub_srv_hw_init() local
562 cw0.offset.quad_part = inst_fb->gpu_addr; in dmub_srv_hw_init()
563 cw0.region.base = DMUB_CW0_BASE; in dmub_srv_hw_init()
564 cw0.region.top = cw0.region.base + inst_fb->size - 1; in dmub_srv_hw_init()
582 dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1); in dmub_srv_hw_init()
584 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); in dmub_srv_hw_init()
|
| H A D | dmub_dcn32.h | 193 const struct dmub_window *cw0,
197 const struct dmub_window *cw0,
|
| H A D | dmub_dcn20.h | 192 const struct dmub_window *cw0,
|
| H A D | dmub_dcn31.h | 194 const struct dmub_window *cw0,
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dmub/ |
| H A D | dmub_srv.h | 334 const struct dmub_window *cw0,
338 const struct dmub_window *cw0,
|