| /openbmc/qemu/target/rx/ |
| H A D | translate.c | 66 static TCGv cpu_regs[16]; variable
73 #define cpu_sp cpu_regs[0]
185 tcg_gen_shli_i32(mem, cpu_regs[ri], size); in rx_gen_regindex()
186 tcg_gen_add_i32(mem, mem, cpu_regs[rb]); in rx_gen_regindex()
197 return cpu_regs[reg]; in rx_index_addr()
200 tcg_gen_addi_i32(mem, cpu_regs[reg], dsp); in rx_index_addr()
205 tcg_gen_addi_i32(mem, cpu_regs[reg], dsp); in rx_index_addr()
232 return cpu_regs[rs]; in rx_load_source()
434 tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); in trans_MOV_rm()
435 rx_gen_st(a->sz, cpu_regs[a->rs], mem); in trans_MOV_rm()
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| /openbmc/linux/drivers/virt/acrn/ |
| H A D | hsm.c | 112 struct acrn_vcpu_regs *cpu_regs; in acrn_dev_ioctl() local
181 cpu_regs = memdup_user((void __user *)ioctl_param, in acrn_dev_ioctl()
183 if (IS_ERR(cpu_regs)) in acrn_dev_ioctl()
184 return PTR_ERR(cpu_regs); in acrn_dev_ioctl()
186 for (i = 0; i < ARRAY_SIZE(cpu_regs->reserved); i++) in acrn_dev_ioctl()
187 if (cpu_regs->reserved[i]) { in acrn_dev_ioctl()
188 kfree(cpu_regs); in acrn_dev_ioctl()
192 for (i = 0; i < ARRAY_SIZE(cpu_regs->vcpu_regs.reserved_32); i++) in acrn_dev_ioctl()
193 if (cpu_regs->vcpu_regs.reserved_32[i]) { in acrn_dev_ioctl()
194 kfree(cpu_regs); in acrn_dev_ioctl()
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| /openbmc/linux/arch/alpha/kernel/ |
| H A D | core_t2.c | 528 struct sable_cpu_csr *cpu_regs; in t2_clear_errors() local
530 cpu_regs = (struct sable_cpu_csr *)T2_CPUn_BASE(cpu); in t2_clear_errors()
532 cpu_regs->sic &= ~SIC_SEIC; in t2_clear_errors()
535 cpu_regs->bcce |= cpu_regs->bcce; in t2_clear_errors()
536 cpu_regs->cbe |= cpu_regs->cbe; in t2_clear_errors()
537 cpu_regs->bcue |= cpu_regs->bcue; in t2_clear_errors()
538 cpu_regs->dter |= cpu_regs->dter; in t2_clear_errors()
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| /openbmc/qemu/target/i386/tcg/ |
| H A D | translate.c | 78 static TCGv cpu_regs[CPU_NB_REGS]; variable
450 dest = dest ? dest : cpu_regs[reg - 4]; in gen_op_deposit_reg_v()
451 tcg_gen_deposit_tl(dest, cpu_regs[reg - 4], t0, 8, 8); in gen_op_deposit_reg_v()
452 return cpu_regs[reg - 4]; in gen_op_deposit_reg_v()
454 dest = dest ? dest : cpu_regs[reg]; in gen_op_deposit_reg_v()
455 tcg_gen_deposit_tl(dest, cpu_regs[reg], t0, 0, 8); in gen_op_deposit_reg_v()
458 dest = dest ? dest : cpu_regs[reg]; in gen_op_deposit_reg_v()
459 tcg_gen_deposit_tl(dest, cpu_regs[reg], t0, 0, 16); in gen_op_deposit_reg_v()
464 dest = dest ? dest : cpu_regs[reg]; in gen_op_deposit_reg_v()
469 dest = dest ? dest : cpu_regs[reg]; in gen_op_deposit_reg_v()
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| H A D | emit.c.inc | 95 tcg_gen_sextract_tl(ofs, cpu_regs[opn], 3, poslen - 3);
291 tcg_gen_sextract_tl(v, cpu_regs[op->n - 4], 8, 8);
293 tcg_gen_extract_tl(v, cpu_regs[op->n - 4], 8, 8);
300 tcg_gen_ext_tl(v, cpu_regs[op->n], op->ot | MO_SIGN);
302 tcg_gen_ext_tl(v, cpu_regs[op->n], op->ot);
306 tcg_gen_mov_tl(v, cpu_regs[op->n]);
1659 * cmpv will be moved to cc_src *after* cpu_regs[] is written back, so use
1662 tcg_gen_ext_tl(cmpv, cpu_regs[decode->op[1].n], ot_full);
1740 tcg_gen_ext_tl(cmpv, cpu_regs[R_EAX], ot);
1763 * directly on cpu_regs. In case rm is part of RAX, note that this
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| /openbmc/linux/net/dsa/ |
| H A D | master.c | 55 struct ethtool_regs *cpu_regs; in dsa_master_get_regs() local
71 cpu_regs = (struct ethtool_regs *)data; in dsa_master_get_regs()
72 data += sizeof(*cpu_regs); in dsa_master_get_regs()
78 cpu_regs->len = len; in dsa_master_get_regs()
79 ds->ops->get_regs(ds, port, cpu_regs, data); in dsa_master_get_regs()
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| /openbmc/linux/include/xen/interface/hvm/ |
| H A D | hvm_vcpu.h | 112 } cpu_regs; member
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| /openbmc/qemu/target/openrisc/ |
| H A D | translate.c | 74 static TCGv cpu_regs[32]; variable
127 cpu_regs[i] = tcg_global_mem_new(tcg_env, in openrisc_translate_init()
166 return cpu_regs[reg]; in cpu_R()
177 dc->R0 = cpu_regs[0]; in check_r0_write()
596 tcg_gen_movi_tl(cpu_regs[9], ret_pc); in trans_l_jal()
638 tcg_gen_movi_tl(cpu_regs[9], dc->base.pc_next + 8); in trans_l_jalr()
1551 dc->R0 = cpu_regs[0]; in openrisc_tr_tb_start()
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| /openbmc/qemu/target/sparc/ |
| H A D | translate.c | 116 static TCGv cpu_regs[32]; variable
339 return cpu_regs[reg]; in gen_load_gpr()
351 tcg_gen_mov_tl(cpu_regs[reg], v); in gen_store_gpr()
359 return cpu_regs[reg]; in gen_dest_gpr()
3693 func(dst, src1, cpu_regs[a->rs2_or_imm]); in do_arith_int()
3765 gen_store_gpr(dc, a->rd, cpu_regs[a->rs2_or_imm]); in TRANS()
3800 tcg_gen_trunc_tl_i32(n2, cpu_regs[a->rs2_or_imm]); in trans_UDIV()
3807 tcg_gen_ext32u_i64(t2, cpu_regs[a->rs2_or_imm]); in trans_UDIV()
3809 tcg_gen_extu_i32_i64(t2, cpu_regs[a->rs2_or_imm]); in trans_UDIV()
3851 src2 = cpu_regs[a->rs2_or_imm]; in trans_UDIVX()
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