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Searched refs:cpu_reg_sp (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/target/arm/tcg/
H A Dtranslate-a64.c356 tcg_gen_extrl_i64_i32(tmp, cpu_reg_sp(s, rn)); in check_lse2_align()
365 tcg_gen_addi_i64(addr, cpu_reg_sp(s, rn), imm); in check_lse2_align()
550 TCGv_i64 cpu_reg_sp(DisasContext *s, int reg) in cpu_reg_sp() function
1652 dst = auth_branch_target(s, cpu_reg(s,a->rn), cpu_reg_sp(s, a->rm), !a->m); in trans_BRA()
1666 dst = auth_branch_target(s, cpu_reg(s, a->rn), cpu_reg_sp(s, a->rm), !a->m); in trans_BLRA()
2688 dirty_addr = cpu_reg_sp(s, rn); in gen_load_exclusive()
2754 clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); in gen_store_exclusive()
2781 gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn != 31, memop); in gen_store_exclusive()
2854 clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn != 31, memop); in gen_compare_and_swap()
2876 clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn != 31, memop); in gen_compare_and_swap_pair()
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H A Dtranslate-a64.h22 TCGv_i64 cpu_reg_sp(DisasContext *s, int reg);
H A Dtranslate-sve.c1143 TCGv_i64 rd = cpu_reg_sp(s, a->rd); in trans_ADDVL()
1144 TCGv_i64 rn = cpu_reg_sp(s, a->rn); in trans_ADDVL()
1156 TCGv_i64 rd = cpu_reg_sp(s, a->rd); in trans_ADDSVL()
1157 TCGv_i64 rn = cpu_reg_sp(s, a->rn); in trans_ADDSVL()
1169 TCGv_i64 rd = cpu_reg_sp(s, a->rd); in trans_ADDPL()
1170 TCGv_i64 rn = cpu_reg_sp(s, a->rn); in trans_ADDPL()
1182 TCGv_i64 rd = cpu_reg_sp(s, a->rd); in trans_ADDSPL()
1183 TCGv_i64 rn = cpu_reg_sp(s, a->rn); in trans_ADDSPL()
2158 vsz, vsz, cpu_reg_sp(s, a->rn)); in trans_DUP_s()
2677 do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, cpu_reg_sp(s, a->rn)); in TRANS_FEAT()
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H A Dtranslate-sme.c233 tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); in trans_LDST1()