| /openbmc/qemu/target/openrisc/ |
| H A D | translate.c | 161 static TCGv cpu_R(DisasContext *dc, int reg) in cpu_R() function
422 gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_add()
429 gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_addc()
436 gen_sub(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_sub()
443 tcg_gen_and_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_and()
450 tcg_gen_or_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_or()
457 tcg_gen_xor_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_xor()
464 tcg_gen_shl_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_sll()
471 tcg_gen_shr_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_srl()
478 tcg_gen_sar_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_sra()
[all …]
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| /openbmc/qemu/target/microblaze/ |
| H A D | translate.c | 49 static TCGv_i32 cpu_R[32]; variable
179 return cpu_R[reg]; in reg_for_read()
194 return cpu_R[reg]; in reg_for_write()
632 tcg_gen_add_i32(tmp, cpu_R[ra], cpu_R[rb]); in DO_TYPEA()
635 tcg_gen_extu_i32_tl(ret, cpu_R[ra]); in DO_TYPEA()
637 tcg_gen_extu_i32_tl(ret, cpu_R[rb]); in DO_TYPEA()
655 tcg_gen_addi_i32(tmp, cpu_R[ra], imm); in compute_ldst_addr_typeb()
675 tcg_gen_extu_i32_tl(ret, cpu_R[rb]); in compute_ldst_addr_ea()
681 tcg_gen_concat_i32_i64(ret, cpu_R[rb], cpu_R[ra]); in compute_ldst_addr_ea()
683 tcg_gen_extu_i32_tl(ret, cpu_R[ra]); in compute_ldst_addr_ea()
[all …]
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| /openbmc/qemu/target/arm/tcg/ |
| H A D | translate.c | 49 static TCGv_i32 cpu_R[16]; variable
65 cpu_R[i] = tcg_global_mem_new_i32(tcg_env, in arm_translate_init()
266 tcg_gen_addi_i32(var, cpu_R[15], (s->pc_curr - s->pc_save) + diff); in gen_pc_plus_diff()
278 tcg_gen_mov_i32(var, cpu_R[reg]); in load_reg_var()
298 tcg_gen_addi_i32(tmp, cpu_R[reg], ofs); in add_reg_for_lit()
320 tcg_gen_mov_i32(cpu_R[reg], var); in store_reg()
752 gen_pc_plus_diff(s, cpu_R[15], diff); in gen_update_pc()
760 tcg_gen_andi_i32(cpu_R[15], var, ~1); in gen_bx()
817 tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], min_magic, excret_label.label); in gen_bx_excret_final_code()
1120 gen_pc_plus_diff(s, cpu_R[15], curr_insn_len(s)); in gen_lookup_tb()
[all …]
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| /openbmc/qemu/target/xtensa/ |
| H A D | translate.c | 80 static TCGv_i32 cpu_R[16]; variable
159 cpu_R[i] = tcg_global_mem_new_i32(tcg_env, in xtensa_translate_init()
249 (void *)"AR 16x32", (void *)cpu_R); in xtensa_get_regfile_by_name()
251 (void *)"AR 32x32", (void *)cpu_R); in xtensa_get_regfile_by_name()
253 (void *)"AR 64x32", (void *)cpu_R); in xtensa_get_regfile_by_name()
399 tcg_gen_movi_i32(cpu_R[callinc << 2], in gen_callw_slot()
1456 tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next); in translate_call0()
1472 tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next); in translate_callx0()
2000 gen_jump(dc, cpu_R[0]); in translate_ret()
2026 tcg_gen_deposit_i32(tmp, tmp, cpu_R[0], 0, 30); in translate_retw()
[all …]
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