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Searched refs:cntr15clk (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_arria10.h31 u32 cntr15clk; member
/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga_arria10_socdk_sdmmc_handoff.dtsi90 cntr15clk-cnt = <900>; /* Field: cntr15clk.cnt */
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_arria10.c771 &clock_manager_base->main_pll.cntr15clk); in cm_full_cfg()