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Searched refs:cmdq (Results 1 – 25 of 72) sorted by relevance

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/openbmc/linux/drivers/infiniband/hw/erdma/
H A Derdma_cmdq.c9 static void arm_cmdq_cq(struct erdma_cmdq *cmdq) in arm_cmdq_cq() argument
11 struct erdma_dev *dev = container_of(cmdq, struct erdma_dev, cmdq); in arm_cmdq_cq()
12 u64 db_data = FIELD_PREP(ERDMA_CQDB_CI_MASK, cmdq->cq.ci) | in arm_cmdq_cq()
14 FIELD_PREP(ERDMA_CQDB_CMDSN_MASK, cmdq->cq.cmdsn) | in arm_cmdq_cq()
15 FIELD_PREP(ERDMA_CQDB_IDX_MASK, cmdq->cq.cmdsn); in arm_cmdq_cq()
17 *cmdq->cq.db_record = db_data; in arm_cmdq_cq()
20 atomic64_inc(&cmdq->cq.armed_num); in arm_cmdq_cq()
23 static void kick_cmdq_db(struct erdma_cmdq *cmdq) in kick_cmdq_db() argument
25 struct erdma_dev *dev = container_of(cmdq, struct erdma_dev, cmdq); in kick_cmdq_db()
26 u64 db_data = FIELD_PREP(ERDMA_CMD_HDR_WQEBB_INDEX_MASK, cmdq->sq.pi); in kick_cmdq_db()
[all …]
H A Derdma.h201 struct erdma_cmdq cmdq; member
264 int erdma_post_cmd_wait(struct erdma_cmdq *cmdq, void *req, u32 req_size,
266 void erdma_cmdq_completion_handler(struct erdma_cmdq *cmdq);
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/falcon/
H A Dcmdq.c26 nvkm_falcon_cmdq_has_room(struct nvkm_falcon_cmdq *cmdq, u32 size, bool *rewind) in nvkm_falcon_cmdq_has_room() argument
28 u32 head = nvkm_falcon_rd32(cmdq->qmgr->falcon, cmdq->head_reg); in nvkm_falcon_cmdq_has_room()
29 u32 tail = nvkm_falcon_rd32(cmdq->qmgr->falcon, cmdq->tail_reg); in nvkm_falcon_cmdq_has_room()
35 free = cmdq->offset + cmdq->size - head; in nvkm_falcon_cmdq_has_room()
40 head = cmdq->offset; in nvkm_falcon_cmdq_has_room()
51 nvkm_falcon_cmdq_push(struct nvkm_falcon_cmdq *cmdq, void *data, u32 size) in nvkm_falcon_cmdq_push() argument
53 struct nvkm_falcon *falcon = cmdq->qmgr->falcon; in nvkm_falcon_cmdq_push()
54 nvkm_falcon_pio_wr(falcon, data, 0, 0, DMEM, cmdq->position, size, 0, false); in nvkm_falcon_cmdq_push()
55 cmdq->position += ALIGN(size, QUEUE_ALIGNMENT); in nvkm_falcon_cmdq_push()
59 nvkm_falcon_cmdq_rewind(struct nvkm_falcon_cmdq *cmdq) in nvkm_falcon_cmdq_rewind() argument
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/openbmc/linux/drivers/mailbox/
H A Dmtk-cmdq-mailbox.c67 struct cmdq *cmdq; member
74 struct cmdq { struct
93 static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable) in cmdq_sw_ddr_enable() argument
95 WARN_ON(clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks)); in cmdq_sw_ddr_enable()
98 writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); in cmdq_sw_ddr_enable()
100 writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); in cmdq_sw_ddr_enable()
102 clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks); in cmdq_sw_ddr_enable()
107 struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox); in cmdq_get_shift_pa() local
109 return cmdq->pdata->shift; in cmdq_get_shift_pa()
113 static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread) in cmdq_thread_suspend() argument
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/openbmc/linux/drivers/crypto/cavium/nitrox/
H A Dnitrox_lib.c25 static int nitrox_cmdq_init(struct nitrox_cmdq *cmdq, int align_bytes) in nitrox_cmdq_init() argument
27 struct nitrox_device *ndev = cmdq->ndev; in nitrox_cmdq_init()
29 cmdq->qsize = (ndev->qlen * cmdq->instr_size) + align_bytes; in nitrox_cmdq_init()
30 cmdq->unalign_base = dma_alloc_coherent(DEV(ndev), cmdq->qsize, in nitrox_cmdq_init()
31 &cmdq->unalign_dma, in nitrox_cmdq_init()
33 if (!cmdq->unalign_base) in nitrox_cmdq_init()
36 cmdq->dma = PTR_ALIGN(cmdq->unalign_dma, align_bytes); in nitrox_cmdq_init()
37 cmdq->base = cmdq->unalign_base + (cmdq->dma - cmdq->unalign_dma); in nitrox_cmdq_init()
38 cmdq->write_idx = 0; in nitrox_cmdq_init()
40 spin_lock_init(&cmdq->cmd_qlock); in nitrox_cmdq_init()
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H A Dnitrox_reqmgr.c230 struct nitrox_cmdq *cmdq) in backlog_list_add() argument
234 spin_lock_bh(&cmdq->backlog_qlock); in backlog_list_add()
235 list_add_tail(&sr->backlog, &cmdq->backlog_head); in backlog_list_add()
236 atomic_inc(&cmdq->backlog_count); in backlog_list_add()
238 spin_unlock_bh(&cmdq->backlog_qlock); in backlog_list_add()
242 struct nitrox_cmdq *cmdq) in response_list_add() argument
246 spin_lock_bh(&cmdq->resp_qlock); in response_list_add()
247 list_add_tail(&sr->response, &cmdq->response_head); in response_list_add()
248 spin_unlock_bh(&cmdq->resp_qlock); in response_list_add()
252 struct nitrox_cmdq *cmdq) in response_list_del() argument
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H A Dnitrox_isr.c32 struct nitrox_cmdq *cmdq = qvec->cmdq; in nps_pkt_slc_isr() local
34 slc_cnts.value = readq(cmdq->compl_cnt_csr_addr); in nps_pkt_slc_isr()
337 qvec->cmdq = &ndev->pkt_inq[qvec->ring]; in nitrox_register_interrupts()
/openbmc/linux/drivers/net/ethernet/brocade/bna/
H A Dbfa_msgq.c31 static void bfa_msgq_cmdq_dbell(struct bfa_msgq_cmdq *cmdq);
32 static void bfa_msgq_cmdq_copy_rsp(struct bfa_msgq_cmdq *cmdq);
43 bfa_fsm_state_decl(cmdq, stopped, struct bfa_msgq_cmdq, enum cmdq_event);
44 bfa_fsm_state_decl(cmdq, init_wait, struct bfa_msgq_cmdq, enum cmdq_event);
45 bfa_fsm_state_decl(cmdq, ready, struct bfa_msgq_cmdq, enum cmdq_event);
46 bfa_fsm_state_decl(cmdq, dbell_wait, struct bfa_msgq_cmdq,
50 cmdq_sm_stopped_entry(struct bfa_msgq_cmdq *cmdq) in cmdq_sm_stopped_entry() argument
54 cmdq->producer_index = 0; in cmdq_sm_stopped_entry()
55 cmdq->consumer_index = 0; in cmdq_sm_stopped_entry()
56 cmdq->flags = 0; in cmdq_sm_stopped_entry()
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/openbmc/linux/drivers/net/ethernet/huawei/hinic/
H A Dhinic_hw_cmdq.c78 #define cmdq_to_cmdqs(cmdq) container_of((cmdq) - (cmdq)->cmdq_type, \ argument
79 struct hinic_cmdqs, cmdq[0])
320 static void cmdq_set_db(struct hinic_cmdq *cmdq, in cmdq_set_db() argument
332 writel(db_info, CMDQ_DB_ADDR(cmdq->db_base, prod_idx)); in cmdq_set_db()
335 static int cmdq_sync_cmd_direct_resp(struct hinic_cmdq *cmdq, in cmdq_sync_cmd_direct_resp() argument
343 struct hinic_wq *wq = cmdq->wq; in cmdq_sync_cmd_direct_resp()
348 spin_lock_bh(&cmdq->cmdq_lock); in cmdq_sync_cmd_direct_resp()
353 spin_unlock_bh(&cmdq->cmdq_lock); in cmdq_sync_cmd_direct_resp()
359 wrapped = cmdq->wrapped; in cmdq_sync_cmd_direct_resp()
364 cmdq->wrapped = !cmdq->wrapped; in cmdq_sync_cmd_direct_resp()
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H A Dhinic_hw_io.c533 enum hinic_cmdq_type cmdq, type; in hinic_io_init() local
565 for (cmdq = HINIC_CMDQ_SYNC; cmdq < HINIC_MAX_CMDQ_TYPES; cmdq++) { in hinic_io_init()
573 func_to_io->cmdq_db_area[cmdq] = db_area; in hinic_io_init()
600 for (type = HINIC_CMDQ_SYNC; type < cmdq; type++) in hinic_io_init()
619 enum hinic_cmdq_type cmdq; in hinic_io_free() local
628 for (cmdq = HINIC_CMDQ_SYNC; cmdq < HINIC_MAX_CMDQ_TYPES; cmdq++) in hinic_io_free()
629 return_db_area(func_to_io, func_to_io->cmdq_db_area[cmdq]); in hinic_io_free()
/openbmc/linux/drivers/accel/ivpu/
H A Divpu_job.c31 static void ivpu_cmdq_ring_db(struct ivpu_device *vdev, struct ivpu_cmdq *cmdq) in ivpu_cmdq_ring_db() argument
33 ivpu_hw_reg_db_set(vdev, cmdq->db_id); in ivpu_cmdq_ring_db()
40 struct ivpu_cmdq *cmdq; in ivpu_cmdq_alloc() local
42 cmdq = kzalloc(sizeof(*cmdq), GFP_KERNEL); in ivpu_cmdq_alloc()
43 if (!cmdq) in ivpu_cmdq_alloc()
46 cmdq->mem = ivpu_bo_alloc_internal(vdev, 0, SZ_4K, DRM_IVPU_BO_WC); in ivpu_cmdq_alloc()
47 if (!cmdq->mem) in ivpu_cmdq_alloc()
50 cmdq->db_id = file_priv->ctx.id + engine * ivpu_get_context_count(vdev); in ivpu_cmdq_alloc()
51 cmdq->entry_count = (u32)((cmdq->mem->base.size - sizeof(struct vpu_job_queue_header)) / in ivpu_cmdq_alloc()
54 cmdq->jobq = (struct vpu_job_queue *)cmdq->mem->kvaddr; in ivpu_cmdq_alloc()
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H A Divpu_mmu.c315 struct ivpu_mmu_queue *q = &mmu->cmdq; in ivpu_mmu_cmdq_alloc()
408 struct ivpu_mmu_queue *cmdq = &vdev->mmu->cmdq; in ivpu_mmu_cmdq_wait_for_cons() local
410 return REGV_POLL(VPU_37XX_HOST_MMU_CMDQ_CONS, cmdq->cons, (cmdq->prod == cmdq->cons), in ivpu_mmu_cmdq_wait_for_cons()
416 struct ivpu_mmu_queue *q = &vdev->mmu->cmdq; in ivpu_mmu_cmdq_cmd_write()
436 struct ivpu_mmu_queue *q = &vdev->mmu->cmdq; in ivpu_mmu_cmdq_sync()
488 memset(mmu->cmdq.base, 0, IVPU_MMU_CMDQ_SIZE); in ivpu_mmu_reset()
489 clflush_cache_range(mmu->cmdq.base, IVPU_MMU_CMDQ_SIZE); in ivpu_mmu_reset()
490 mmu->cmdq.prod = 0; in ivpu_mmu_reset()
491 mmu->cmdq.cons = 0; in ivpu_mmu_reset()
512 REGV_WR64(VPU_37XX_HOST_MMU_CMDQ_BASE, mmu->cmdq.dma_q); in ivpu_mmu_reset()
/openbmc/linux/drivers/infiniband/hw/bnxt_re/
H A Dqplib_rcfw.c114 struct bnxt_qplib_cmdq_ctx *cmdq; in bnxt_re_is_fw_stalled() local
118 cmdq = &rcfw->cmdq; in bnxt_re_is_fw_stalled()
120 if (time_after(jiffies, cmdq->last_seen + in bnxt_re_is_fw_stalled()
125 jiffies_to_msecs(jiffies - cmdq->last_seen), in bnxt_re_is_fw_stalled()
147 struct bnxt_qplib_cmdq_ctx *cmdq; in __wait_for_resp() local
151 cmdq = &rcfw->cmdq; in __wait_for_resp()
155 if (test_bit(ERR_DEVICE_DETACHED, &cmdq->flags)) in __wait_for_resp()
157 if (test_bit(FIRMWARE_STALL_DETECTED, &cmdq->flags)) in __wait_for_resp()
160 wait_event_timeout(cmdq->waitq, in __wait_for_resp()
162 test_bit(ERR_DEVICE_DETACHED, &cmdq->flags), in __wait_for_resp()
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/openbmc/linux/drivers/net/ethernet/hisilicon/hns3/hns3_common/
H A Dhclge_comm_cmd.c529 struct hclge_comm_cmq *cmdq = &hw->cmq; in hclge_comm_cmd_uninit() local
538 spin_lock_bh(&cmdq->csq.lock); in hclge_comm_cmd_uninit()
539 spin_lock(&cmdq->crq.lock); in hclge_comm_cmd_uninit()
541 spin_unlock(&cmdq->crq.lock); in hclge_comm_cmd_uninit()
542 spin_unlock_bh(&cmdq->csq.lock); in hclge_comm_cmd_uninit()
544 hclge_comm_free_cmd_desc(&cmdq->csq); in hclge_comm_cmd_uninit()
545 hclge_comm_free_cmd_desc(&cmdq->crq); in hclge_comm_cmd_uninit()
550 struct hclge_comm_cmq *cmdq = &hw->cmq; in hclge_comm_cmd_queue_init() local
554 spin_lock_init(&cmdq->csq.lock); in hclge_comm_cmd_queue_init()
555 spin_lock_init(&cmdq->crq.lock); in hclge_comm_cmd_queue_init()
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/sec2/
H A Dbase.c45 struct nvkm_falcon_cmdq *cmdq = sec2->cmdq; in nvkm_sec2_fini() local
56 ret = nvkm_falcon_cmdq_send(cmdq, &cmd, nvkm_sec2_finimsg, sec2, in nvkm_sec2_fini()
68 nvkm_falcon_cmdq_fini(cmdq); in nvkm_sec2_fini()
119 nvkm_falcon_cmdq_del(&sec2->cmdq); in nvkm_sec2_dtor()
159 (ret = nvkm_falcon_cmdq_new(sec2->qmgr, "cmdq", &sec2->cmdq)) || in nvkm_sec2_new_()
H A Dga102.c49 nvkm_falcon_cmdq_init(sec2->cmdq, msg.queue_info[i].index, in ga102_sec2_initmsg()
103 return nvkm_falcon_cmdq_send(sec2->cmdq, &cmd.cmd.hdr, in ga102_sec2_acr_bootstrap_falcon()
136 .cmdq = { 0xc00, 0xc04, 8 },
H A Dgp102.c71 return nvkm_falcon_cmdq_send(sec2->cmdq, &cmd.cmd.hdr, in gp102_sec2_acr_bootstrap_falcon()
142 nvkm_falcon_cmdq_init(sec2->cmdq, in gp102_sec2_initmsg()
214 .cmdq = { 0xa00, 0xa04, 8 },
/openbmc/linux/drivers/iommu/arm/arm-smmu-v3/
H A Darm-smmu-v3.c350 return &smmu->cmdq; in arm_smmu_get_cmdq()
429 __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq.q); in arm_smmu_cmdq_skip_err()
444 static void arm_smmu_cmdq_shared_lock(struct arm_smmu_cmdq *cmdq) in arm_smmu_cmdq_shared_lock() argument
454 if (atomic_fetch_inc_relaxed(&cmdq->lock) >= 0) in arm_smmu_cmdq_shared_lock()
458 val = atomic_cond_read_relaxed(&cmdq->lock, VAL >= 0); in arm_smmu_cmdq_shared_lock()
459 } while (atomic_cmpxchg_relaxed(&cmdq->lock, val, val + 1) != val); in arm_smmu_cmdq_shared_lock()
462 static void arm_smmu_cmdq_shared_unlock(struct arm_smmu_cmdq *cmdq) in arm_smmu_cmdq_shared_unlock() argument
464 (void)atomic_dec_return_release(&cmdq->lock); in arm_smmu_cmdq_shared_unlock()
467 static bool arm_smmu_cmdq_shared_tryunlock(struct arm_smmu_cmdq *cmdq) in arm_smmu_cmdq_shared_tryunlock() argument
469 if (atomic_read(&cmdq->lock) == 1) in arm_smmu_cmdq_shared_tryunlock()
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/openbmc/qemu/hw/arm/
H A Dsmmuv3.c300 s->cmdq.base = deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS); in smmuv3_init_regs()
301 s->cmdq.prod = 0; in smmuv3_init_regs()
302 s->cmdq.cons = 0; in smmuv3_init_regs()
303 s->cmdq.entry_size = sizeof(struct Cmd); in smmuv3_init_regs()
1298 SMMUQueue *q = &s->cmdq; in smmuv3_cmdq_consume()
1536 s->cmdq.base = data; in smmu_writell()
1537 s->cmdq.log2size = extract64(s->cmdq.base, 0, 5); in smmu_writell()
1538 if (s->cmdq.log2size > SMMU_CMDQS) { in smmu_writell()
1539 s->cmdq.log2size = SMMU_CMDQS; in smmu_writell()
1623 s->cmdq.base = deposit64(s->cmdq.base, 0, 32, data); in smmu_writel()
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/openbmc/linux/drivers/atm/
H A Dfore200e.c556 struct host_cmdq* cmdq = &fore200e->host_cmdq; in fore200e_pca_prom_read() local
557 struct host_cmdq_entry* entry = &cmdq->host_entry[ cmdq->head ]; in fore200e_pca_prom_read()
562 FORE200E_NEXT_ENTRY(cmdq->head, QUEUE_SIZE_CMD); in fore200e_pca_prom_read()
1225 struct host_cmdq* cmdq = &fore200e->host_cmdq; in fore200e_activate_vcin() local
1226 struct host_cmdq_entry* entry = &cmdq->host_entry[ cmdq->head ]; in fore200e_activate_vcin()
1233 FORE200E_NEXT_ENTRY(cmdq->head, QUEUE_SIZE_CMD); in fore200e_activate_vcin()
1669 struct host_cmdq* cmdq = &fore200e->host_cmdq; in fore200e_getstats() local
1670 struct host_cmdq_entry* entry = &cmdq->host_entry[ cmdq->head ]; in fore200e_getstats()
1686 FORE200E_NEXT_ENTRY(cmdq->head, QUEUE_SIZE_CMD); in fore200e_getstats()
1715 struct host_cmdq* cmdq = &fore200e->host_cmdq;
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/openbmc/linux/drivers/media/platform/mediatek/mdp3/
H A DMakefile4 mtk-mdp3-y += mtk-mdp3-comp.o mtk-mdp3-cmdq.o
/openbmc/linux/drivers/soc/mediatek/
H A DMakefile2 obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
H A Dgp102.c38 .cmdq = { 0x4a0, 0x4b0, 4 },
/openbmc/linux/drivers/gpu/drm/nouveau/include/nvkm/engine/
H A Dsec2.h17 struct nvkm_falcon_cmdq *cmdq; member
/openbmc/qemu/hw/audio/
H A Dvirtio-snd.c747 while (!QTAILQ_EMPTY(&s->cmdq)) { in virtio_snd_process_cmdq()
748 cmd = QTAILQ_FIRST(&s->cmdq); in virtio_snd_process_cmdq()
753 QTAILQ_REMOVE(&s->cmdq, cmd, next); in virtio_snd_process_cmdq()
788 QTAILQ_INSERT_TAIL(&s->cmdq, cmd, next); in virtio_snd_handle_ctrl()
1090 QTAILQ_INIT(&vsnd->cmdq); in virtio_snd_realize()
1357 while (!QTAILQ_EMPTY(&vsnd->cmdq)) { in virtio_snd_reset()
1358 cmd = QTAILQ_FIRST(&vsnd->cmdq); in virtio_snd_reset()
1359 QTAILQ_REMOVE(&vsnd->cmdq, cmd, next); in virtio_snd_reset()

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