Home
last modified time | relevance | path

Searched refs:clock_manager_base (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_gen5.c12 static const struct socfpga_clock_manager *clock_manager_base = variable
21 writel(val, &clock_manager_base->bypass); in cm_write_bypass()
28 writel(val, &clock_manager_base->ctrl); in cm_write_ctrl()
82 readl(&clock_manager_base->per_pll.en), in cm_basic_init()
83 &clock_manager_base->per_pll.en); in cm_basic_init()
92 &clock_manager_base->main_pll.en); in cm_basic_init()
94 writel(0, &clock_manager_base->sdr_pll.en); in cm_basic_init()
97 writel(0, &clock_manager_base->per_pll.en); in cm_basic_init()
106 &clock_manager_base->main_pll.vco); in cm_basic_init()
109 &clock_manager_base->per_pll.vco); in cm_basic_init()
[all …]
H A Dclock_manager_s10.c15 static const struct socfpga_clock_manager *clock_manager_base = variable
26 writel(val, &clock_manager_base->main_pll.bypass); in cm_write_bypass_mainpll()
32 writel(val, &clock_manager_base->per_pll.bypass); in cm_write_bypass_perpll()
39 writel(val, &clock_manager_base->ctrl); in cm_write_ctrl()
71 &clock_manager_base->main_pll.pllglob); in cm_basic_init()
72 writel(cfg->main_pll_fdbck, &clock_manager_base->main_pll.fdbck); in cm_basic_init()
73 writel(vcocalib, &clock_manager_base->main_pll.vcocalib); in cm_basic_init()
74 writel(cfg->main_pll_pllc0, &clock_manager_base->main_pll.pllc0); in cm_basic_init()
75 writel(cfg->main_pll_pllc1, &clock_manager_base->main_pll.pllc1); in cm_basic_init()
76 writel(cfg->main_pll_nocdiv, &clock_manager_base->main_pll.nocdiv); in cm_basic_init()
[all …]
H A Dclock_manager_arria10.c234 static const struct socfpga_clock_manager *clock_manager_base = variable
554 &clock_manager_base->main_pll.vco1); in cm_pll_ramp_main()
559 main_cfg->vco1_numer, &clock_manager_base->main_pll.vco1); in cm_pll_ramp_main()
584 &clock_manager_base->per_pll.vco1); in cm_pll_ramp_periph()
589 per_cfg->vco1_numer, &clock_manager_base->per_pll.vco1); in cm_pll_ramp_periph()
641 &clock_manager_base->main_pll.enr); in cm_full_cfg()
644 writel(0, &clock_manager_base->per_pll.en); in cm_full_cfg()
648 &clock_manager_base->main_pll.bypasss); in cm_full_cfg()
650 &clock_manager_base->per_pll.bypasss); in cm_full_cfg()
660 &clock_manager_base->main_pll.vco0); in cm_full_cfg()
[all …]
H A Dclock_manager.c13 static const struct socfpga_clock_manager *clock_manager_base = variable
22 inter_val = readl(&clock_manager_base->inter) & mask; in cm_wait_for_lock()
24 inter_val = readl(&clock_manager_base->stat) & mask; in cm_wait_for_lock()
39 return wait_for_bit_le32(&clock_manager_base->stat, in cm_wait_for_fsm()
/openbmc/u-boot/drivers/mmc/
H A Dsocfpga_dw_mmc.c21 static const struct socfpga_clock_manager *clock_manager_base = variable
59 clrbits_le32(&clock_manager_base->per_pll.en, in socfpga_dwmci_clksel()
70 setbits_le32(&clock_manager_base->per_pll.en, in socfpga_dwmci_clksel()