Searched refs:clock_ctl (Results 1 – 6 of 6) sorted by relevance
| /openbmc/linux/arch/mips/ath25/ |
| H A D | ar2315.c | 204 static unsigned __init ar2315_sys_clk(u32 clock_ctl) in ar2315_sys_clk() argument
218 switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) { in ar2315_sys_clk()
234 cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV); in ar2315_sys_clk()
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| /openbmc/linux/drivers/hid/ |
| H A D | hid-ft260.c | 148 u8 clock_ctl; /* 0 - 12MHz, 1 - 24MHz, 2 - 48MHz */ member
179 u8 clock_ctl; /* 0 - 12MHz, 1 - 24MHz, 2 - 48MHz */ member
798 ft260_dbg("clock_ctl: 0x%02x\n", cfg.clock_ctl); in ft260_is_interface_enabled()
921 FT260_SSTAT_ATTR_SHOW(clock_ctl);
922 FT260_BYTE_ATTR_STORE(clock_ctl, ft260_set_system_clock_report,
924 static DEVICE_ATTR_RW(clock_ctl);
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| /openbmc/qemu/include/hw/sd/ |
| H A D | allwinner-sdhost.h | 90 uint32_t clock_ctl; /**< Clock Control */ member
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| /openbmc/linux/drivers/memstick/host/ |
| H A D | jmb38x_ms.c | 679 unsigned int clock_ctl = CLOCK_CONTROL_BY_MMIO, clock_delay = 0; in jmb38x_ms_set_param() local
725 clock_ctl |= CLOCK_CONTROL_40MHZ; in jmb38x_ms_set_param()
732 clock_ctl |= CLOCK_CONTROL_40MHZ; in jmb38x_ms_set_param()
738 clock_ctl |= CLOCK_CONTROL_50MHZ; in jmb38x_ms_set_param()
745 writel(clock_ctl, host->addr + CLOCK_CONTROL); in jmb38x_ms_set_param()
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| /openbmc/qemu/hw/sd/ |
| H A D | allwinner-sdhost.c | 472 res = s->clock_ctl; in allwinner_sdhost_read()
631 s->clock_ctl = value; in allwinner_sdhost_write()
778 VMSTATE_UINT32(clock_ctl, AwSdHostState),
848 s->clock_ctl = REG_SD_CKCR_RST; in allwinner_sdhost_reset()
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| /openbmc/linux/drivers/net/ethernet/broadcom/ |
| H A D | tg3.c | 6146 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL); in tg3_refclk_write() local
6148 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP); in tg3_refclk_write()
6151 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME); in tg3_refclk_write()
6259 u32 clock_ctl; in tg3_ptp_enable() local
6272 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL); in tg3_ptp_enable()
6273 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK; in tg3_ptp_enable()
6301 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0); in tg3_ptp_enable()
6304 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl); in tg3_ptp_enable()
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