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Searched refs:clk_phase (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/mmc/host/
H A Ddw_mmc-pltfm.c74 u32 clk_phase[2] = {0}, reg_offset, reg_shift; in dw_mci_socfpga_priv_init() local
77 rc = of_property_read_variable_u32_array(np, "clk-phase-sd-hs", &clk_phase[0], 2, 0); in dw_mci_socfpga_priv_init()
90 for (i = 0; i < ARRAY_SIZE(clk_phase); i++) in dw_mci_socfpga_priv_init()
91 clk_phase[i] /= SOCFPGA_DW_MMC_CLK_PHASE_STEP; in dw_mci_socfpga_priv_init()
93 hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1], reg_shift); in dw_mci_socfpga_priv_init()
H A Dsdhci-of-arasan.c1223 u32 clk_phase[2] = {0}; in arasan_dt_read_clk_phase() local
1230 ret = of_property_read_variable_u32_array(np, prop, &clk_phase[0], in arasan_dt_read_clk_phase()
1240 clk_data->clk_phase_in[timing] = clk_phase[0]; in arasan_dt_read_clk_phase()
1241 clk_data->clk_phase_out[timing] = clk_phase[1]; in arasan_dt_read_clk_phase()
/openbmc/linux/include/trace/events/
H A Dclk.h198 DECLARE_EVENT_CLASS(clk_phase,
217 DEFINE_EVENT(clk_phase, clk_set_phase,
224 DEFINE_EVENT(clk_phase, clk_set_phase_complete,
/openbmc/linux/sound/soc/codecs/
H A Dlm49453.c1146 int clk_phase = 0; in lm49453_set_dai_fmt() local
1173 clk_phase = (1 << 5); in lm49453_set_dai_fmt()
1178 clk_phase = (1 << 5); in lm49453_set_dai_fmt()
1187 (aif_val | mode | clk_phase)); in lm49453_set_dai_fmt()