Searched refs:cl_value (Results 1 – 1 of 1) sorted by relevance
| /openbmc/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 94 u32 if_id, u32 cl_value, u32 cwl_value);
344 u32 cl_value = 0, cwl_val = 0; in hws_ddr3_tip_init_controller() local
510 cl_value = in hws_ddr3_tip_init_controller()
518 cl_value, cwl_val)); in hws_ddr3_tip_init_controller()
525 ((cl_mask_table[cl_value] & 0x1) << 2) | in hws_ddr3_tip_init_controller()
526 ((cl_mask_table[cl_value] & 0xe) << 3); in hws_ddr3_tip_init_controller()
565 cl_value, cwl_val); in hws_ddr3_tip_init_controller()
1199 u32 cl_value = 0, cwl_value = 0, mem_mask = 0, val = 0, in ddr3_tip_freq_set() local
1256 cl_value = in ddr3_tip_freq_set()
1262 cl_value = mv_ddr_cl_calc(tm->timing_data[MV_DDR_TAA_MIN], tclk); in ddr3_tip_freq_set()
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