Searched refs:cfsr (Results 1 – 5 of 5) sorted by relevance
247 env->v7m.cfsr[secure] |= R_V7M_CFSR_MLSPERR_MASK; in v7m_stack_write()251 env->v7m.cfsr[secure] |= R_V7M_CFSR_MSTKERR_MASK; in v7m_stack_write()264 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_LSPERR_MASK; in v7m_stack_write()267 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_STKERR_MASK; in v7m_stack_write()326 env->v7m.cfsr[secure] |= R_V7M_CFSR_MUNSTKERR_MASK; in v7m_stack_read()338 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_UNSTKERR_MASK; in v7m_stack_read()383 env->v7m.cfsr[is_secure] |= R_V7M_CFSR_NOCP_MASK; in HELPER()387 env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_NOCP_MASK; in HELPER()804 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_STKOF_MASK; in v7m_push_callee_stack()1231 env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_STKOF_MASK; in v7m_push_stack()[all …]
37 uint32_t cfsr; /* offset 0x28: Configurable Fault Status Reg */ member
2307 val = s->cpu->env.v7m.cfsr[attrs.secure]; in nvic_sysreg_read()2312 val |= s->cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK; in nvic_sysreg_read()2441 s->cpu->env.v7m.cfsr[attrs.secure] &= ~value; in nvic_sysreg_write()2446 s->cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK); in nvic_sysreg_write()
522 VMSTATE_UINT32(env.v7m.cfsr[M_REG_NS], ARMCPU),720 VMSTATE_UINT32(env.v7m.cfsr[M_REG_S], ARMCPU),
547 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ member