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Searched refs:cfgr (Results 1 – 22 of 22) sorted by relevance

/openbmc/u-boot/drivers/gpio/
H A Datmel_pio4.c63 writel(reg, &port_base->cfgr); in atmel_pio4_config_io_func()
140 writel(reg, &port_base->cfgr); in atmel_pio4_set_pio_output()
166 writel(reg, &port_base->cfgr); in atmel_pio4_get_pio_input()
201 clrbits_le32(&port_base->cfgr, in atmel_pio4_direction_input()
217 clrsetbits_le32(&port_base->cfgr, in atmel_pio4_direction_output()
263 return (readl(&port_base->cfgr) & in atmel_pio4_get_function()
/openbmc/u-boot/drivers/clk/
H A Dclk_stm32f.c153 writel(0, &regs->cfgr); /* Reset CFGR */ in configure_clocks()
165 setbits_le32(&regs->cfgr, (( in configure_clocks()
249 clrbits_le32(&regs->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); in configure_clocks()
250 setbits_le32(&regs->cfgr, RCC_CFGR_SW_PLL); in configure_clocks()
252 while ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) != in configure_clocks()
339 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_get_hclk_rate()
354 (readl(&regs->cfgr) & RCC_CFGR_APB1_PSC_MASK) in stm32_get_apb_shift()
358 (readl(&regs->cfgr) & RCC_CFGR_APB2_PSC_MASK) in stm32_get_apb_shift()
403 if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) == in stm32_clk_get_rate()
H A Dclk_stm32h7.c124 u32 cfgr; /* 0x10 Clock Configuration Register */ member
360 writel(0, &regs->cfgr); in configure_clocks()
417 clrsetbits_le32(&regs->cfgr, RCC_CFGR_SW_MASK, RCC_CFGR_SW_PLL1); in configure_clocks()
418 while ((readl(&regs->cfgr) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL1) in configure_clocks()
596 if (readl(&regs->cfgr) & RCC_CFGR_TIMPRE) in stm32_get_timer_rate()
644 source = readl(&regs->cfgr) & RCC_CFGR_SW_MASK; in stm32_clk_get_rate()
/openbmc/qemu/hw/misc/
H A Dstm32l4x5_rcc.c447 if (FIELD_EX32(s->cfgr, CFGR, SWS) != 0b11) { in rcc_update_cr_register()
467 if (FIELD_EX32(s->cfgr, CFGR, SWS) != 0b10 && in rcc_update_cr_register()
491 if (FIELD_EX32(s->cfgr, CFGR, SWS) == 0b01 || in rcc_update_cr_register()
518 if (FIELD_EX32(s->cfgr, CFGR, SWS) == 0b00 || in rcc_update_cr_register()
545 val = FIELD_EX32(s->cfgr, CFGR, MCOPRE); in rcc_update_cfgr_register()
557 val = FIELD_EX32(s->cfgr, CFGR, MCOSEL); in rcc_update_cfgr_register()
577 val = FIELD_EX32(s->cfgr, CFGR, PPRE2); in rcc_update_cfgr_register()
587 val = FIELD_EX32(s->cfgr, CFGR, PPRE1); in rcc_update_cfgr_register()
597 val = FIELD_EX32(s->cfgr, CFGR, HPRE); in rcc_update_cfgr_register()
607 val = FIELD_EX32(s->cfgr, CFGR, SW); in rcc_update_cfgr_register()
[all …]
/openbmc/linux/drivers/pwm/
H A Dpwm-stm32-lp.c40 u32 val, mask, cfgr, presc = 0; in stm32_pwm_lp_apply() local
90 ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr); in stm32_pwm_lp_apply()
94 if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) || in stm32_pwm_lp_apply()
95 (FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) != state->polarity)) { in stm32_pwm_lp_apply()
/openbmc/linux/drivers/mmc/host/
H A Dmmci_stm32_sdmmc.c489 u32 cfgr; in sdmmc_dlyb_mp15_set_cfg() local
493 cfgr = FIELD_PREP(DLYB_CFGR_UNIT_MASK, unit) | in sdmmc_dlyb_mp15_set_cfg()
495 writel_relaxed(cfgr, dlyb->base + DLYB_CFGR); in sdmmc_dlyb_mp15_set_cfg()
506 u32 cfgr; in sdmmc_dlyb_mp15_prepare() local
512 ret = readl_relaxed_poll_timeout(dlyb->base + DLYB_CFGR, cfgr, in sdmmc_dlyb_mp15_prepare()
513 (cfgr & DLYB_CFGR_LNGF), in sdmmc_dlyb_mp15_prepare()
518 i, cfgr); in sdmmc_dlyb_mp15_prepare()
522 lng = FIELD_GET(DLYB_CFGR_LNG_MASK, cfgr); in sdmmc_dlyb_mp15_prepare()
/openbmc/linux/sound/soc/stm/
H A Dstm32_i2s.c726 u32 cfgr, cfgr_mask, cfg1; in stm32_i2s_configure() local
732 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_16); in stm32_i2s_configure()
736 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_32) | in stm32_i2s_configure()
746 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_SLAVE); in stm32_i2s_configure()
749 cfgr |= I2S_CGFR_FIXCH; in stm32_i2s_configure()
752 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_MASTER); in stm32_i2s_configure()
757 cfgr_mask, cfgr); in stm32_i2s_configure()
/openbmc/linux/drivers/perf/
H A Darm_smmuv3_pmu.c851 u32 cfgr, reg_size; in smmu_pmu_probe() local
883 cfgr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CFGR); in smmu_pmu_probe()
886 if (cfgr & SMMU_PMCG_CFGR_RELOC_CTRS) { in smmu_pmu_probe()
903 smmu_pmu->num_counters = FIELD_GET(SMMU_PMCG_CFGR_NCTR, cfgr) + 1; in smmu_pmu_probe()
905 smmu_pmu->global_filter = !!(cfgr & SMMU_PMCG_CFGR_SID_FILTER_TYPE); in smmu_pmu_probe()
907 reg_size = FIELD_GET(SMMU_PMCG_CFGR_SIZE, cfgr); in smmu_pmu_probe()
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_mc.h20 u32 cfgr; /* 0x04 Configuration Register */ member
H A Datmel_pio4.h14 u32 cfgr; /* 0x04 PIO Configuration Register */ member
/openbmc/u-boot/include/
H A Dstm32_rcc.h62 u32 cfgr; /* RCC clock configuration */ member
/openbmc/qemu/include/hw/misc/
H A Dstm32l4x5_rcc.h189 uint32_t cfgr; member
/openbmc/u-boot/drivers/pinctrl/
H A Dpinctrl-at91-pio4.c144 writel(conf, &bank_base->cfgr); in atmel_pinctrl_set_state()
/openbmc/linux/drivers/net/ethernet/freescale/enetc/
H A Denetc_pf.c384 u32 cfgr; in enetc_pf_set_vf_spoofchk() local
389 cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1)); in enetc_pf_set_vf_spoofchk()
390 cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0); in enetc_pf_set_vf_spoofchk()
391 enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr); in enetc_pf_set_vf_spoofchk()
/openbmc/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex5.dtsi271 clock-names = "core-clk", "cfgr-clk";
288 clock-names = "core-clk", "cfgr-clk";
/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-at91-pio4.c145 u32 cfgr[ATMEL_PIO_NPINS_PER_BANK]; member
1010 atmel_pioctrl->pm_suspend_backup[i].cfgr[j] = in atmel_pctrl_suspend()
1033 atmel_pioctrl->pm_suspend_backup[i].cfgr[j]); in atmel_pctrl_resume()
/openbmc/linux/arch/arc/boot/dts/
H A Dhsdk.dts332 clock-names = "core-clk", "cfgr-clk";
/openbmc/linux/arch/riscv/boot/dts/thead/
H A Dth1520.dtsi284 clock-names = "core-clk", "cfgr-clk";
/openbmc/linux/arch/riscv/boot/dts/canaan/
H A Dk210.dtsi163 clock-names = "core-clk", "cfgr-clk";
/openbmc/linux/drivers/net/ethernet/freescale/
H A Dfec_main.c1182 u32 cfgr; in fec_restart() local
1193 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) in fec_restart()
1196 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; in fec_restart()
1197 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); in fec_restart()
/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi960 clock-names = "core-clk", "cfgr-clk";
/openbmc/linux/drivers/net/wireless/cisco/
H A Dairo.c1829 ConfigRid cfgr; in writeConfigRid() local
1837 cfgr = ai->config; in writeConfigRid()
1839 if ((cfgr.opmode & MODE_CFG_MASK) == MODE_STA_IBSS) in writeConfigRid()
1844 return PC4500_writerid(ai, RID_CONFIG, &cfgr, sizeof(cfgr), lock); in writeConfigRid()