Searched refs:cfg_tmp (Results 1 – 3 of 3) sorted by relevance
286 u32 cfg_tmp; in do_enabled_lanes_reset() local294 cfg_tmp = cfg & srds_prctl_info[pos].mask; in do_enabled_lanes_reset()295 cfg_tmp >>= srds_prctl_info[pos].shift; in do_enabled_lanes_reset()297 for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) { in do_enabled_lanes_reset()408 u32 cfg_tmp; in setup_serdes_volt() local443 cfg_tmp = cfg_rcwsrds1 & 0x3; in setup_serdes_volt()444 do_pll_reset(cfg_tmp, serdes1_base); in setup_serdes_volt()448 cfg_tmp = cfg_rcwsrds1 & 0xC; in setup_serdes_volt()449 cfg_tmp >>= 2; in setup_serdes_volt()450 do_pll_reset(cfg_tmp, serdes2_base); in setup_serdes_volt()[all …]
150 u32 cfg_tmp, reg = 0; in setup_serdes_volt() local176 cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in setup_serdes_volt()177 cfg_tmp >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; in setup_serdes_volt()179 for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) { in setup_serdes_volt()186 cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; in setup_serdes_volt()187 cfg_tmp >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT; in setup_serdes_volt()189 for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) { in setup_serdes_volt()198 cfg_tmp = (cfg_rcw5 >> 22) & 0x3; in setup_serdes_volt()199 for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) { in setup_serdes_volt()214 cfg_tmp = (cfg_rcw5 >> 20) & 0x3; in setup_serdes_volt()[all …]
446 struct cscfg_config_desc *config_desc, *cfg_tmp; in cscfg_unload_owned_cfgs_feats() local463 list_for_each_entry_safe(config_desc, cfg_tmp, &cscfg_mgr->config_desc_list, item) { in cscfg_unload_owned_cfgs_feats()