Searched refs:cdclk_state (Results 1 – 9 of 9) sorted by relevance
2661 static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) in intel_compute_min_cdclk() argument2663 struct intel_atomic_state *state = cdclk_state->base.state; in intel_compute_min_cdclk()2678 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) in intel_compute_min_cdclk()2681 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; in intel_compute_min_cdclk()2683 ret = intel_atomic_lock_global_state(&cdclk_state->base); in intel_compute_min_cdclk()2692 if (cdclk_state->bw_min_cdclk != min_cdclk) { in intel_compute_min_cdclk()2695 cdclk_state->bw_min_cdclk = min_cdclk; in intel_compute_min_cdclk()2697 ret = intel_atomic_lock_global_state(&cdclk_state->base); in intel_compute_min_cdclk()2703 min_cdclk = max(cdclk_state->force_min_cdclk, in intel_compute_min_cdclk()2704 cdclk_state->bw_min_cdclk); in intel_compute_min_cdclk()[all …]
241 const struct intel_cdclk_state *cdclk_state; in hsw_ips_compute_config() local243 cdclk_state = intel_atomic_get_cdclk_state(state); in hsw_ips_compute_config()244 if (IS_ERR(cdclk_state)) in hsw_ips_compute_config()245 return PTR_ERR(cdclk_state); in hsw_ips_compute_config()248 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100) in hsw_ips_compute_config()
81 struct intel_cdclk_state *cdclk_state; in intel_display_driver_init_hw() local86 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_display_driver_init_hw()90 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; in intel_display_driver_init_hw()
157 struct intel_cdclk_state *cdclk_state = in intel_crtc_disable_noatomic_complete() local178 cdclk_state->min_cdclk[pipe] = 0; in intel_crtc_disable_noatomic_complete()179 cdclk_state->min_voltage_level[pipe] = 0; in intel_crtc_disable_noatomic_complete()180 cdclk_state->active_pipes &= ~BIT(pipe); in intel_crtc_disable_noatomic_complete()677 struct intel_cdclk_state *cdclk_state = in intel_modeset_readout_hw_state() local714 cdclk_state->active_pipes = active_pipes; in intel_modeset_readout_hw_state()867 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; in intel_modeset_readout_hw_state()868 cdclk_state->min_voltage_level[crtc->pipe] = in intel_modeset_readout_hw_state()
260 const struct intel_cdclk_state *cdclk_state; in intel_plane_calc_min_cdclk() local285 cdclk_state = intel_atomic_get_cdclk_state(state); in intel_plane_calc_min_cdclk()286 if (IS_ERR(cdclk_state)) in intel_plane_calc_min_cdclk()287 return PTR_ERR(cdclk_state); in intel_plane_calc_min_cdclk()298 cdclk_state->min_cdclk[crtc->pipe]) in intel_plane_calc_min_cdclk()306 cdclk_state->min_cdclk[crtc->pipe]); in intel_plane_calc_min_cdclk()
1140 const struct intel_cdclk_state *cdclk_state; in intel_bw_calc_min_cdclk() local1185 cdclk_state = intel_atomic_get_cdclk_state(state); in intel_bw_calc_min_cdclk()1186 if (IS_ERR(cdclk_state)) in intel_bw_calc_min_cdclk()1187 return PTR_ERR(cdclk_state); in intel_bw_calc_min_cdclk()1197 if (new_min_cdclk <= cdclk_state->bw_min_cdclk) in intel_bw_calc_min_cdclk()1202 new_min_cdclk, cdclk_state->bw_min_cdclk); in intel_bw_calc_min_cdclk()
910 struct intel_cdclk_state *cdclk_state; in glk_force_audio_cdclk_commit() local918 cdclk_state = intel_atomic_get_cdclk_state(state); in glk_force_audio_cdclk_commit()919 if (IS_ERR(cdclk_state)) in glk_force_audio_cdclk_commit()920 return PTR_ERR(cdclk_state); in glk_force_audio_cdclk_commit()922 cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0; in glk_force_audio_cdclk_commit()
1161 const struct intel_cdclk_state *cdclk_state; in intel_fbc_check_plane() local1163 cdclk_state = intel_atomic_get_cdclk_state(state); in intel_fbc_check_plane()1164 if (IS_ERR(cdclk_state)) in intel_fbc_check_plane()1165 return PTR_ERR(cdclk_state); in intel_fbc_check_plane()1167 if (crtc_state->pixel_rate >= cdclk_state->logical.cdclk * 95 / 100) { in intel_fbc_check_plane()
4197 const struct intel_cdclk_state *cdclk_state) in hsw_ips_linetime_wm() argument4207 cdclk_state->logical.cdclk); in hsw_ips_linetime_wm()4240 const struct intel_cdclk_state *cdclk_state; in hsw_compute_linetime_wm() local4250 cdclk_state = intel_atomic_get_cdclk_state(state); in hsw_compute_linetime_wm()4251 if (IS_ERR(cdclk_state)) in hsw_compute_linetime_wm()4252 return PTR_ERR(cdclk_state); in hsw_compute_linetime_wm()4255 cdclk_state); in hsw_compute_linetime_wm()