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Searched refs:bus_cnt (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c768 u32 bus_cnt; in ddr3_tip_calc_cs_mask() local
783 for (bus_cnt = 0; bus_cnt < octets_per_if_num; bus_cnt++) { in ddr3_tip_calc_cs_mask()
784 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_calc_cs_mask()
787 as_bus_params[bus_cnt].cs_bitmask; in ddr3_tip_calc_cs_mask()
789 as_bus_params[bus_cnt].cs_bitmask; in ddr3_tip_calc_cs_mask()
793 as_bus_params[bus_cnt].cs_bitmask; in ddr3_tip_calc_cs_mask()
807 u32 reg_data = 0, temp = 0, iter, if_id, bus_cnt; in ddr3_tip_dynamic_write_leveling() local
926 for (bus_cnt = 0; bus_cnt < octets_per_if_num; bus_cnt++) { in ddr3_tip_dynamic_write_leveling()
927 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_dynamic_write_leveling()
930 mask_results_pup_reg_map[bus_cnt], in ddr3_tip_dynamic_write_leveling()
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H A Dddr3_training.c345 u32 bus_cnt = 0, adll_tap = 0; in hws_ddr3_tip_init_controller() local
477 for (bus_cnt = 0; in hws_ddr3_tip_init_controller()
478 bus_cnt < octets_per_if_num; in hws_ddr3_tip_init_controller()
479 bus_cnt++) { in hws_ddr3_tip_init_controller()
480 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in hws_ddr3_tip_init_controller()
483 as_bus_params[bus_cnt].cs_bitmask; in hws_ddr3_tip_init_controller()
678 u32 data_value = 0, bus_cnt = 0; in ddr3_tip_rev2_rank_control() local
682 for (bus_cnt = 0; bus_cnt < octets_per_if_num; bus_cnt++) { in ddr3_tip_rev2_rank_control()
683 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_rev2_rank_control()
684 data_value |= tm->interface_params[if_id].as_bus_params[bus_cnt]. in ddr3_tip_rev2_rank_control()
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H A Dddr3_training_ip_engine.c1460 u32 bus_cnt = 0, if_id, dev_num = 0; in ddr3_tip_load_phy_values() local
1466 for (bus_cnt = 0; bus_cnt < octets_per_if_num; bus_cnt++) { in ddr3_tip_load_phy_values()
1467 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_load_phy_values()
1471 ACCESS_TYPE_UNICAST, bus_cnt, in ddr3_tip_load_phy_values()
1474 &phy_reg_bk[if_id][bus_cnt] in ddr3_tip_load_phy_values()
1478 ACCESS_TYPE_UNICAST, bus_cnt, in ddr3_tip_load_phy_values()
1481 &phy_reg_bk[if_id][bus_cnt] in ddr3_tip_load_phy_values()
1485 ACCESS_TYPE_UNICAST, bus_cnt, in ddr3_tip_load_phy_values()
1488 &phy_reg_bk[if_id][bus_cnt] in ddr3_tip_load_phy_values()
1494 bus_cnt, DDR_PHY_DATA, in ddr3_tip_load_phy_values()
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H A Dddr3_debug.c834 u32 bus_cnt = 0, if_id, data_p1, data_p2, ui_data3, dev_num = 0; in ddr3_tip_print_adll() local
840 for (bus_cnt = 0; bus_cnt < octets_per_if_num; in ddr3_tip_print_adll()
841 bus_cnt++) { in ddr3_tip_print_adll()
842 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_print_adll()
845 ACCESS_TYPE_UNICAST, bus_cnt, in ddr3_tip_print_adll()
849 bus_cnt, DDR_PHY_DATA, 0x2, &data_p2)); in ddr3_tip_print_adll()
852 bus_cnt, DDR_PHY_DATA, 0x3, &ui_data3)); in ddr3_tip_print_adll()
855 if_id, bus_cnt, data_p1, data_p2, in ddr3_tip_print_adll()