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Searched refs:bit1 (Results 1 – 25 of 52) sorted by relevance

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/openbmc/linux/include/linux/
H A Dmman.h134 #define _calc_vm_trans(x, bit1, bit2) \ argument
135 ((!(bit1) || !(bit2)) ? 0 : \
136 ((bit1) <= (bit2) ? ((x) & (bit1)) * ((bit2) / (bit1)) \
137 : ((x) & (bit1)) / ((bit1) / (bit2))))
/openbmc/u-boot/tools/
H A Dvybridimage.c43 uint8_t bit1 = (byte & (1 << 1)) ? 1 : 0; in vybridimage_sw_ecc() local
53 res |= ((bit7 ^ bit5 ^ bit4 ^ bit2 ^ bit1) << 1); in vybridimage_sw_ecc()
54 res |= ((bit7 ^ bit6 ^ bit5 ^ bit1 ^ bit0) << 2); in vybridimage_sw_ecc()
56 res |= ((bit6 ^ bit4 ^ bit3 ^ bit2 ^ bit1 ^ bit0) << 4); in vybridimage_sw_ecc()
/openbmc/libpldm/include/libpldm/
H A Dpldm_types.h11 uint8_t bit1 : 1; member
38 uint8_t bit1 : 1; member
60 uint8_t bit1 : 1; member
98 uint8_t bit1 : 1; member
/openbmc/linux/Documentation/driver-api/mtd/
H A Dnand_ecc.rst45 byte 0: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp2 rp4 ... rp14
46 byte 1: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp1 rp2 rp4 ... rp14
47 byte 2: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp3 rp4 ... rp14
48 byte 3: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp1 rp3 rp4 ... rp14
49 byte 4: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp2 rp5 ... rp14
51 byte 254: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp3 rp5 ... rp15
52 byte 255: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp1 rp3 rp5 ... rp15
67 Similarly cp1 is the sum of all bit1, bit3, bit5 and bit7.
69 - cp2 is the parity over bit0, bit1, bit4 and bit5
71 - cp4 is the parity over bit0, bit1, bit2 and bit3.
[all …]
/openbmc/linux/include/uapi/linux/
H A Dioam6.h61 bit1:1, member
98 bit1:1, member
/openbmc/linux/Documentation/leds/
H A Dleds-mlxcpld.rst53 [bit3,bit2,bit1,bit0] or
98 [bit3,bit2,bit1,bit0] or
110 [bit3,bit2,bit1,bit0]:
/openbmc/u-boot/board/Seagate/nas220/
H A Dkwbimage.cfg65 # bit1-0: 00, Cs0width=x8
100 # bit1: 0, DDR drive strenght normal
124 # bit1: 0, Write Protect disabled
138 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
/openbmc/u-boot/board/Seagate/dockstar/
H A Dkwbimage.cfg63 # bit1-0: 00, Cs0width=x8
97 # bit1: 0, DDR drive strenght normal
125 # bit1: 0, Write Protect disabled
138 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
/openbmc/u-boot/board/Synology/ds109/
H A Dkwbimage.cfg64 # bit1-0: 01, Cs0width=x8
98 # bit1: 0, DDR drive strenght normal
126 # bit1: 0, Write Protect disabled
141 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
/openbmc/u-boot/board/Seagate/goflexhome/
H A Dkwbimage.cfg66 # bit1-0: 00, Cs0width=x8
100 # bit1: 0, DDR drive strenght normal
128 # bit1: 0, Write Protect disabled
141 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
/openbmc/u-boot/board/Marvell/dreamplug/
H A Dkwbimage.cfg61 # bit1-0: 01, Cs0width=x8
95 # bit1: 0, DDR drive strenght normal
123 # bit1: 0, Write Protect disabled
136 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
/openbmc/u-boot/board/Marvell/sheevaplug/
H A Dkwbimage.cfg60 # bit1-0: 00, Cs0width=x8
94 # bit1: 0, DDR drive strenght normal
122 # bit1: 0, Write Protect disabled
135 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
/openbmc/u-boot/board/Marvell/guruplug/
H A Dkwbimage.cfg60 # bit1-0: 01, Cs0width=x8
94 # bit1: 0, DDR drive strenght normal
122 # bit1: 0, Write Protect disabled
135 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
/openbmc/u-boot/board/LaCie/netspace_v2/
H A Dkwbimage.cfg60 # bit1-0: 00, Cs0width=x8
94 # bit1: 1, DDR drive strenght reduced
122 # bit1: 0, Write Protect disabled
136 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
H A Dkwbimage-is2.cfg60 # bit1-0: 00, Cs0width=x8
94 # bit1: 1, DDR drive strenght reduced
122 # bit1: 0, Write Protect disabled
136 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
H A Dkwbimage-ns2l.cfg60 # bit1-0: 00, Cs0width=x8
94 # bit1: 1, DDR drive strenght reduced
122 # bit1: 0, Write Protect disabled
136 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
/openbmc/u-boot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg64 # bit1-0: 00, Cs0width=x8
98 # bit1: 0, DDR drive strenght normal
126 # bit1: 0, Write Protect disabled
144 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
/openbmc/u-boot/board/iomega/iconnect/
H A Dkwbimage.cfg60 # bit1-0: 00, Cs0width (x8)
94 # bit1: 0, DDR drive strenght normal
122 # bit1: 0x0, Write Protect disabled
140 # bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above
/openbmc/u-boot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg60 # bit1-0: 01, Cs0width=x16
94 # bit1: 1, DDR drive strenght reduced
122 # bit1: 0, Write Protect disabled
136 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage.cfg81 # bit1-0: 01, Cs0width=x16
106 # bit1: 0, DDR drive strenght normal
133 # bit1: 0, Write Protect disabled
147 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
H A Dkwbimage-memphis.cfg84 # bit1-0: 01, Cs0width=x16
109 # bit1: 1, DDR drive strenght reduced
148 # bit1: 0, Write Protect disabled
162 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
/openbmc/u-boot/board/raidsonic/ib62x0/
H A Dkwbimage.cfg61 # bit1-0: 00, Cs0width (x8)
95 # bit1: 0, DDR drive strenght normal
123 # bit1: 0x0, Write Protect disabled
141 # bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg70 # bit1-0: 0, Cs0width=x8
104 # bit1: 0, DRAM drive strength normal
144 # bit1: 0, Write Protect disabled
152 # bit1: 0, Write Protect disabled
169 # bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg75 # bit1-0: 1, Cs0width=x16
113 # bit1: 1, DRAM drive strength reduced
160 # bit1: 0, Write Protect disabled
188 # bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
H A Dkwbimage-lsxhl.cfg75 # bit1-0: 0, Cs0width=x8
113 # bit1: 1, DRAM drive strength reduced
160 # bit1: 0, Write Protect disabled
188 # bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register

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