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Searched refs:ast_set_index_reg_mask (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/ast/
H A Dast_dp.c40 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5, (u8) ~ASTDP_HOST_EDID_READ_DONE_MASK, in ast_astdp_read_edid()
47 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE4, in ast_astdp_read_edid()
106 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5, (u8) ~ASTDP_HOST_EDID_READ_DONE_MASK, in ast_astdp_read_edid()
112 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5, in ast_astdp_read_edid()
156 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5, in ast_dp_launch()
174 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE3, (u8) ~AST_DP_PHY_SLEEP, bE3); in ast_dp_power_on_off()
186 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE3, (u8) ~AST_DP_VIDEO_ENABLE, on); in ast_dp_set_on_off()
270 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE0, ASTDP_AND_CLEAR_MASK, in ast_dp_set_mode()
272 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE1, ASTDP_AND_CLEAR_MASK, ASTDP_MISC1); in ast_dp_set_mode()
273 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE2, ASTDP_AND_CLEAR_MASK, ModeIdx); in ast_dp_set_mode()
H A Dast_mode.c305 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x01, 0xdf, stdtable->seq[0]); in ast_set_std_reg()
312 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); in ast_set_std_reg()
349 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); in ast_set_crtc_reg()
354 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp); in ast_set_crtc_reg()
359 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp); in ast_set_crtc_reg()
364 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp); in ast_set_crtc_reg()
371 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f)); in ast_set_crtc_reg()
376 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp); in ast_set_crtc_reg()
381 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05)); in ast_set_crtc_reg()
383 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC); in ast_set_crtc_reg()
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H A Dast_dp501.c36 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_ack()
44 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_nack()
81 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x40); in set_cmd_trigger()
86 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x00); in clear_cmd_trigger()
113 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data); in ast_write_cmd()
135 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data); in ast_write_data()
169 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, 0x00);
416 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); in ast_init_dvo()
445 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x00); in ast_init_analog()
H A Dast_i2c.c38 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7); in ast_i2c_setsda()
54 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7); in ast_i2c_setscl()
H A Dast_post.c61 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info); in ast_set_def_ext_reg()
70 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01); in ast_set_def_ext_reg()
71 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00); in ast_set_def_ext_reg()
77 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg); in ast_set_def_ext_reg()
352 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); /* Enable DVO */ in ast_post_gpu()
H A Dast_drv.h334 static inline void ast_set_index_reg_mask(struct ast_device *ast, u32 base, u8 index, in ast_set_index_reg_mask() function