Searched refs:asic_blank_end (Results 1 – 6 of 6) sorted by relevance
164 uint32_t asic_blank_end; in optc1_program_timing() local200 asic_blank_end = asic_blank_start - in optc1_program_timing()207 OTG_H_BLANK_END, asic_blank_end); in optc1_program_timing()238 asic_blank_end = asic_blank_start - in optc1_program_timing()245 OTG_V_BLANK_END, asic_blank_end); in optc1_program_timing()344 uint32_t asic_blank_end; in optc1_set_vtg_params() local358 asic_blank_end = v_init - in optc1_set_vtg_params()364 vertical_line_start = asic_blank_end - optc1->vstartup_start + 1; in optc1_set_vtg_params()372 if ((optc1->vstartup_start/2)*2 > asic_blank_end) in optc1_set_vtg_params()
3701 int asic_blank_end; in dcn10_get_vupdate_offset_from_vsync() local3713 asic_blank_end = (patched_crtc_timing.v_total - in dcn10_get_vupdate_offset_from_vsync()3718 return asic_blank_end - in dcn10_get_vupdate_offset_from_vsync()
762 int vesa_sync_start, asic_blank_end, asic_blank_start; in dcn_validate_bandwidth() local1220 asic_blank_end = (pipe->stream->timing.v_total - in dcn_validate_bandwidth()1225 asic_blank_start = asic_blank_end + in dcn_validate_bandwidth()1232 pipe->pipe_dlg_param.vblank_end = asic_blank_end; in dcn_validate_bandwidth()
3544 uint32_t asic_blank_end = 0; in adaptive_sync_override_dp_info_packets_sdp_line_num() 3553 asic_blank_end = (asic_blank_start - tg->v_border_bottom - in adaptive_sync_override_dp_info_packets_sdp_line_num() 3556 if (pipe_dlg_param->vstartup_start > asic_blank_end) { in adaptive_sync_override_dp_info_packets_sdp_line_num() 3557 v_update = (tg->v_total - (pipe_dlg_param->vstartup_start - asic_blank_end)); in adaptive_sync_override_dp_info_packets_sdp_line_num() 3543 uint32_t asic_blank_end = 0; adaptive_sync_override_dp_info_packets_sdp_line_num() local
1105 uint32_t asic_blank_end = 0; in dcn20_adjust_freesync_v_startup() local1124 asic_blank_end = asic_blank_start - in dcn20_adjust_freesync_v_startup()1129 newVstartup = asic_blank_end + (patched_crtc_timing.v_total - asic_blank_start); in dcn20_adjust_freesync_v_startup()
1318 uint32_t asic_blank_end = 0; in dcn20_adjust_freesync_v_startup() local1337 asic_blank_end = asic_blank_start - in dcn20_adjust_freesync_v_startup()1342 newVstartup = asic_blank_end + (patched_crtc_timing.v_total - asic_blank_start); in dcn20_adjust_freesync_v_startup()