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Searched refs:amdgpu_ring_write (Results 1 – 25 of 39) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Djpeg_v1_0.c186 amdgpu_ring_write(ring, in jpeg_v1_0_decode_ring_insert_start()
188 amdgpu_ring_write(ring, 0x68e04); in jpeg_v1_0_decode_ring_insert_start()
190 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_insert_start()
191 amdgpu_ring_write(ring, 0x80010000); in jpeg_v1_0_decode_ring_insert_start()
205 amdgpu_ring_write(ring, in jpeg_v1_0_decode_ring_insert_end()
207 amdgpu_ring_write(ring, 0x68e04); in jpeg_v1_0_decode_ring_insert_end()
209 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_insert_end()
210 amdgpu_ring_write(ring, 0x00010000); in jpeg_v1_0_decode_ring_insert_end()
230 amdgpu_ring_write(ring, in jpeg_v1_0_decode_ring_emit_fence()
232 amdgpu_ring_write(ring, seq); in jpeg_v1_0_decode_ring_emit_fence()
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H A Djpeg_v2_0.c445 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_insert_start()
447 amdgpu_ring_write(ring, 0x68e04); in jpeg_v2_0_dec_ring_insert_start()
449 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_insert_start()
451 amdgpu_ring_write(ring, 0x80010000); in jpeg_v2_0_dec_ring_insert_start()
463 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_insert_end()
465 amdgpu_ring_write(ring, 0x68e04); in jpeg_v2_0_dec_ring_insert_end()
467 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_insert_end()
469 amdgpu_ring_write(ring, 0x00010000); in jpeg_v2_0_dec_ring_insert_end()
487 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
489 amdgpu_ring_write(ring, seq); in jpeg_v2_0_dec_ring_emit_fence()
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H A Dvcn_sw_ring.c32 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE); in vcn_dec_sw_ring_emit_fence()
33 amdgpu_ring_write(ring, addr); in vcn_dec_sw_ring_emit_fence()
34 amdgpu_ring_write(ring, upper_32_bits(addr)); in vcn_dec_sw_ring_emit_fence()
35 amdgpu_ring_write(ring, seq); in vcn_dec_sw_ring_emit_fence()
36 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP); in vcn_dec_sw_ring_emit_fence()
41 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); in vcn_dec_sw_ring_insert_end()
49 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB); in vcn_dec_sw_ring_emit_ib()
50 amdgpu_ring_write(ring, vmid); in vcn_dec_sw_ring_emit_ib()
51 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vcn_dec_sw_ring_emit_ib()
52 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vcn_dec_sw_ring_emit_ib()
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H A Djpeg_v4_0_3.c658 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v4_0_3_dec_ring_insert_start()
660 amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ in jpeg_v4_0_3_dec_ring_insert_start()
662 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v4_0_3_dec_ring_insert_start()
664 amdgpu_ring_write(ring, 0x80004000); in jpeg_v4_0_3_dec_ring_insert_start()
676 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v4_0_3_dec_ring_insert_end()
678 amdgpu_ring_write(ring, 0x62a04); in jpeg_v4_0_3_dec_ring_insert_end()
680 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v4_0_3_dec_ring_insert_end()
682 amdgpu_ring_write(ring, 0x00004000); in jpeg_v4_0_3_dec_ring_insert_end()
700 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, in jpeg_v4_0_3_dec_ring_emit_fence()
702 amdgpu_ring_write(ring, seq); in jpeg_v4_0_3_dec_ring_emit_fence()
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H A Duvd_v6_0.c183 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); in uvd_v6_0_enc_ring_test_ring()
486 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
487 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
490 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
491 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
494 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
495 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
498 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v6_0_hw_init()
499 amdgpu_ring_write(ring, 0x8); in uvd_v6_0_hw_init()
501 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v6_0_hw_init()
[all …]
H A Duvd_v5_0.c174 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
175 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
178 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
179 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
182 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
183 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
186 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v5_0_hw_init()
187 amdgpu_ring_write(ring, 0x8); in uvd_v5_0_hw_init()
189 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v5_0_hw_init()
190 amdgpu_ring_write(ring, 3); in uvd_v5_0_hw_init()
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H A Duvd_v3_1.c94 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); in uvd_v3_1_ring_emit_ib()
95 amdgpu_ring_write(ring, ib->gpu_addr); in uvd_v3_1_ring_emit_ib()
96 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); in uvd_v3_1_ring_emit_ib()
97 amdgpu_ring_write(ring, ib->length_dw); in uvd_v3_1_ring_emit_ib()
115 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v3_1_ring_emit_fence()
116 amdgpu_ring_write(ring, seq); in uvd_v3_1_ring_emit_fence()
117 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v3_1_ring_emit_fence()
118 amdgpu_ring_write(ring, addr & 0xffffffff); in uvd_v3_1_ring_emit_fence()
119 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v3_1_ring_emit_fence()
120 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); in uvd_v3_1_ring_emit_fence()
[all …]
H A Duvd_v4_2.c177 amdgpu_ring_write(ring, tmp); in uvd_v4_2_hw_init()
178 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v4_2_hw_init()
181 amdgpu_ring_write(ring, tmp); in uvd_v4_2_hw_init()
182 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v4_2_hw_init()
185 amdgpu_ring_write(ring, tmp); in uvd_v4_2_hw_init()
186 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v4_2_hw_init()
189 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v4_2_hw_init()
190 amdgpu_ring_write(ring, 0x8); in uvd_v4_2_hw_init()
192 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v4_2_hw_init()
193 amdgpu_ring_write(ring, 3); in uvd_v4_2_hw_init()
[all …]
H A Dsdma_v2_4.c230 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v2_4_ring_insert_nop()
233 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v2_4_ring_insert_nop()
256 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v2_4_ring_emit_ib()
259 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v2_4_ring_emit_ib()
260 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v2_4_ring_emit_ib()
261 amdgpu_ring_write(ring, ib->length_dw); in sdma_v2_4_ring_emit_ib()
262 amdgpu_ring_write(ring, 0); in sdma_v2_4_ring_emit_ib()
263 amdgpu_ring_write(ring, 0); in sdma_v2_4_ring_emit_ib()
283 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v2_4_ring_emit_hdp_flush()
286 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); in sdma_v2_4_ring_emit_hdp_flush()
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H A Dsi_dma.c72 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); in si_dma_ring_emit_ib()
73 amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vmid, 0)); in si_dma_ring_emit_ib()
74 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in si_dma_ring_emit_ib()
75 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in si_dma_ring_emit_ib()
97 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0)); in si_dma_ring_emit_fence()
98 amdgpu_ring_write(ring, addr & 0xfffffffc); in si_dma_ring_emit_fence()
99 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); in si_dma_ring_emit_fence()
100 amdgpu_ring_write(ring, seq); in si_dma_ring_emit_fence()
104 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0)); in si_dma_ring_emit_fence()
105 amdgpu_ring_write(ring, addr & 0xfffffffc); in si_dma_ring_emit_fence()
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H A Duvd_v7_0.c191 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); in uvd_v7_0_enc_ring_test_ring()
553 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
554 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
558 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
559 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
563 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
564 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
567 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
569 amdgpu_ring_write(ring, 0x8); in uvd_v7_0_hw_init()
571 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
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H A Dsdma_v6_0.c86 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE)); in sdma_v6_0_ring_init_cond_exec()
87 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); in sdma_v6_0_ring_init_cond_exec()
88 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); in sdma_v6_0_ring_init_cond_exec()
89 amdgpu_ring_write(ring, 1); in sdma_v6_0_ring_init_cond_exec()
91 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ in sdma_v6_0_ring_init_cond_exec()
231 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v6_0_ring_insert_nop()
234 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v6_0_ring_insert_nop()
265 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v6_0_ring_emit_ib()
268 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v6_0_ring_emit_ib()
269 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v6_0_ring_emit_ib()
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H A Dcik_sdma.c204 amdgpu_ring_write(ring, ring->funcs->nop | in cik_sdma_ring_insert_nop()
207 amdgpu_ring_write(ring, ring->funcs->nop); in cik_sdma_ring_insert_nop()
231 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); in cik_sdma_ring_emit_ib()
232 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ in cik_sdma_ring_emit_ib()
233 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); in cik_sdma_ring_emit_ib()
234 amdgpu_ring_write(ring, ib->length_dw); in cik_sdma_ring_emit_ib()
256 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); in cik_sdma_ring_emit_hdp_flush()
257 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); in cik_sdma_ring_emit_hdp_flush()
258 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); in cik_sdma_ring_emit_hdp_flush()
259 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_ring_emit_hdp_flush()
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H A Dvcn_v2_0.c1382 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_insert_start()
1383 amdgpu_ring_write(ring, 0); in vcn_v2_0_dec_ring_insert_start()
1384 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_start()
1385 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); in vcn_v2_0_dec_ring_insert_start()
1399 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_end()
1400 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1)); in vcn_v2_0_dec_ring_insert_end()
1419 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0)); in vcn_v2_0_dec_ring_insert_nop()
1420 amdgpu_ring_write(ring, 0); in vcn_v2_0_dec_ring_insert_nop()
1440 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0)); in vcn_v2_0_dec_ring_emit_fence()
1441 amdgpu_ring_write(ring, seq); in vcn_v2_0_dec_ring_emit_fence()
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H A Dgfx_v7_0.c2039 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v7_0_ring_test_ring()
2040 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START); in gfx_v7_0_ring_test_ring()
2041 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v7_0_ring_test_ring()
2082 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_hdp_flush()
2083 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ in gfx_v7_0_ring_emit_hdp_flush()
2086 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); in gfx_v7_0_ring_emit_hdp_flush()
2087 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); in gfx_v7_0_ring_emit_hdp_flush()
2088 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2089 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2090 amdgpu_ring_write(ring, 0x20); /* poll interval */ in gfx_v7_0_ring_emit_hdp_flush()
[all …]
H A Dsdma_v5_2.c96 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); in sdma_v5_2_ring_init_cond_exec()
97 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_2_ring_init_cond_exec()
98 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_2_ring_init_cond_exec()
99 amdgpu_ring_write(ring, 1); in sdma_v5_2_ring_init_cond_exec()
101 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ in sdma_v5_2_ring_init_cond_exec()
221 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v5_2_ring_insert_nop()
224 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v5_2_ring_insert_nop()
255 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v5_2_ring_emit_ib()
258 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_2_ring_emit_ib()
259 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v5_2_ring_emit_ib()
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H A Dvcn_v1_0.c1432 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_start()
1434 amdgpu_ring_write(ring, 0); in vcn_v1_0_dec_ring_insert_start()
1435 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_start()
1437 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); in vcn_v1_0_dec_ring_insert_start()
1451 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_end()
1453 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); in vcn_v1_0_dec_ring_insert_end()
1473 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_fence()
1475 amdgpu_ring_write(ring, seq); in vcn_v1_0_dec_ring_emit_fence()
1476 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_fence()
1478 amdgpu_ring_write(ring, addr & 0xffffffff); in vcn_v1_0_dec_ring_emit_fence()
[all …]
H A Dsdma_v3_0.c404 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v3_0_ring_insert_nop()
407 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v3_0_ring_insert_nop()
430 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v3_0_ring_emit_ib()
433 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v3_0_ring_emit_ib()
434 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v3_0_ring_emit_ib()
435 amdgpu_ring_write(ring, ib->length_dw); in sdma_v3_0_ring_emit_ib()
436 amdgpu_ring_write(ring, 0); in sdma_v3_0_ring_emit_ib()
437 amdgpu_ring_write(ring, 0); in sdma_v3_0_ring_emit_ib()
457 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v3_0_ring_emit_hdp_flush()
460 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); in sdma_v3_0_ring_emit_hdp_flush()
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H A Dsdma_v5_0.c256 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); in sdma_v5_0_ring_init_cond_exec()
257 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_0_ring_init_cond_exec()
258 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_0_ring_init_cond_exec()
259 amdgpu_ring_write(ring, 1); in sdma_v5_0_ring_init_cond_exec()
261 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ in sdma_v5_0_ring_init_cond_exec()
406 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v5_0_ring_insert_nop()
409 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v5_0_ring_insert_nop()
440 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v5_0_ring_emit_ib()
443 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_0_ring_emit_ib()
444 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v5_0_ring_emit_ib()
[all …]
H A Dgfx_v8_0.c850 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v8_0_ring_test_ring()
851 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START); in gfx_v8_0_ring_test_ring()
852 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v8_0_ring_test_ring()
4161 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_cp_gfx_start()
4162 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v8_0_cp_gfx_start()
4164 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in gfx_v8_0_cp_gfx_start()
4165 amdgpu_ring_write(ring, 0x80000000); in gfx_v8_0_cp_gfx_start()
4166 amdgpu_ring_write(ring, 0x80000000); in gfx_v8_0_cp_gfx_start()
4171 amdgpu_ring_write(ring, in gfx_v8_0_cp_gfx_start()
4174 amdgpu_ring_write(ring, in gfx_v8_0_cp_gfx_start()
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H A Dgfx_v6_0.c1780 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_test_ring()
1781 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START); in gfx_v6_0_ring_test_ring()
1782 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v6_0_ring_test_ring()
1799 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v6_0_ring_emit_vgt_flush()
1800 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | in gfx_v6_0_ring_emit_vgt_flush()
1810 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_emit_fence()
1811 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); in gfx_v6_0_ring_emit_fence()
1812 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_fence()
1813 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in gfx_v6_0_ring_emit_fence()
1814 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | in gfx_v6_0_ring_emit_fence()
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H A Dgfx_v11_0.c137 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx11_kiq_set_resources()
138 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | in gfx11_kiq_set_resources()
140 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx11_kiq_set_resources()
141 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx11_kiq_set_resources()
142 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ in gfx11_kiq_set_resources()
143 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ in gfx11_kiq_set_resources()
144 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx11_kiq_set_resources()
145 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx11_kiq_set_resources()
172 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx11_kiq_map_queues()
174 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx11_kiq_map_queues()
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H A Dgfx_v9_0.c771 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v9_0_kiq_set_resources()
772 amdgpu_ring_write(kiq_ring, in gfx_v9_0_kiq_set_resources()
776 amdgpu_ring_write(kiq_ring, in gfx_v9_0_kiq_set_resources()
778 amdgpu_ring_write(kiq_ring, in gfx_v9_0_kiq_set_resources()
780 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ in gfx_v9_0_kiq_set_resources()
781 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ in gfx_v9_0_kiq_set_resources()
782 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx_v9_0_kiq_set_resources()
783 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx_v9_0_kiq_set_resources()
793 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx_v9_0_kiq_map_queues()
795 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx_v9_0_kiq_map_queues()
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H A Dgfx_v9_4_3.c63 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v9_4_3_kiq_set_resources()
64 amdgpu_ring_write(kiq_ring, in gfx_v9_4_3_kiq_set_resources()
68 amdgpu_ring_write(kiq_ring, in gfx_v9_4_3_kiq_set_resources()
70 amdgpu_ring_write(kiq_ring, in gfx_v9_4_3_kiq_set_resources()
72 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ in gfx_v9_4_3_kiq_set_resources()
73 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ in gfx_v9_4_3_kiq_set_resources()
74 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx_v9_4_3_kiq_set_resources()
75 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx_v9_4_3_kiq_set_resources()
86 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx_v9_4_3_kiq_map_queues()
88 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx_v9_4_3_kiq_map_queues()
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H A Dsdma_v4_4_2.c293 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v4_4_2_ring_insert_nop()
296 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v4_4_2_ring_insert_nop()
319 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v4_4_2_ring_emit_ib()
322 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v4_4_2_ring_emit_ib()
323 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v4_4_2_ring_emit_ib()
324 amdgpu_ring_write(ring, ib->length_dw); in sdma_v4_4_2_ring_emit_ib()
325 amdgpu_ring_write(ring, 0); in sdma_v4_4_2_ring_emit_ib()
326 amdgpu_ring_write(ring, 0); in sdma_v4_4_2_ring_emit_ib()
336 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v4_4_2_wait_reg_mem()
342 amdgpu_ring_write(ring, addr0); in sdma_v4_4_2_wait_reg_mem()
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