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Searched refs:access_type (Results 1 – 25 of 140) sorted by relevance

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/openbmc/qemu/target/ppc/
H A Dmmu-radix64.c115 static void ppc_radix64_raise_segi(PowerPCCPU *cpu, MMUAccessType access_type, in ppc_radix64_raise_segi() argument
121 switch (access_type) { in ppc_radix64_raise_segi()
138 static inline const char *access_str(MMUAccessType access_type) in access_str() argument
140 return access_type == MMU_DATA_LOAD ? "reading" : in access_str()
141 (access_type == MMU_DATA_STORE ? "writing" : "execute"); in access_str()
144 static void ppc_radix64_raise_si(PowerPCCPU *cpu, MMUAccessType access_type, in ppc_radix64_raise_si() argument
151 __func__, access_str(access_type), in ppc_radix64_raise_si()
154 switch (access_type) { in ppc_radix64_raise_si()
175 static void ppc_radix64_raise_hsi(PowerPCCPU *cpu, MMUAccessType access_type, in ppc_radix64_raise_hsi() argument
184 env->error_code = access_type; in ppc_radix64_raise_hsi()
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H A Dmmu-booke.c73 MMUAccessType access_type) in mmu40x_get_physical_address() argument
90 __func__, i, zsel, zpr, access_type, tlb->attr); in mmu40x_get_physical_address()
117 if (check_prot_access_type(*prot, access_type)) { in mmu40x_get_physical_address()
159 MMUAccessType access_type, int i) in mmubooke_check_tlb() argument
167 if ((access_type == MMU_INST_FETCH ? in mmubooke_check_tlb()
179 if (check_prot_access_type(*prot, access_type)) { in mmubooke_check_tlb()
185 return access_type == MMU_INST_FETCH ? -3 : -2; in mmubooke_check_tlb()
190 MMUAccessType access_type) in mmubooke_get_physical_address() argument
198 access_type, i); in mmubooke_get_physical_address()
266 static uint32_t mmubooke206_esr(int mmu_idx, MMUAccessType access_type) in mmubooke206_esr() argument
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H A Dmmu-hash32.c52 MMUAccessType access_type, int *prot, in ppc_hash32_bat_lookup() argument
57 bool ifetch = access_type == MMU_INST_FETCH; in ppc_hash32_bat_lookup()
115 MMUAccessType access_type, in ppc_hash32_direct_store() argument
124 if (access_type == MMU_INST_FETCH) { in ppc_hash32_direct_store()
137 switch (guest_visible ? env->access_type : ACCESS_INT) { in ppc_hash32_direct_store()
151 if (access_type == MMU_DATA_STORE) { in ppc_hash32_direct_store()
171 if (access_type == MMU_DATA_STORE) { in ppc_hash32_direct_store()
186 if (check_prot_access_type(*prot, access_type)) { in ppc_hash32_direct_store()
195 if (access_type == MMU_DATA_STORE) { in ppc_hash32_direct_store()
294 bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, in ppc_hash32_xlate() argument
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H A Dmmu_common.c89 target_ulong eaddr, MMUAccessType access_type, in ppc6xx_tlb_check() argument
95 bool is_code = (access_type == MMU_INST_FETCH); in ppc6xx_tlb_check()
118 access_type == MMU_DATA_STORE ? 'S' : 'L', in ppc6xx_tlb_check()
119 access_type == MMU_INST_FETCH ? 'I' : 'D'); in ppc6xx_tlb_check()
136 if (check_prot_access_type(*prot, access_type)) { in ppc6xx_tlb_check()
153 if (access_type == MMU_DATA_STORE && ret == 0) { in ppc6xx_tlb_check()
191 target_ulong eaddr, MMUAccessType access_type, in get_bat_6xx_tlb() argument
197 bool ifetch = access_type == MMU_INST_FETCH; in get_bat_6xx_tlb()
226 if (check_prot_access_type(*prot, access_type)) { in get_bat_6xx_tlb()
264 MMUAccessType access_type, int type) in mmu6xx_get_physical_address() argument
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H A Duser_only_helper.c27 MMUAccessType access_type, in ppc_cpu_record_sigsegv() argument
40 if (access_type == MMU_INST_FETCH) { in ppc_cpu_record_sigsegv()
46 if (access_type == MMU_DATA_STORE) { in ppc_cpu_record_sigsegv()
H A Dinternal.h240 static inline int check_prot_access_type(int prot, MMUAccessType access_type) in check_prot_access_type() argument
242 return prot & (1 << access_type); in check_prot_access_type()
247 bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
273 MMUAccessType access_type,
277 MMUAccessType access_type, int mmu_idx,
280 MMUAccessType access_type, int mmu_idx,
284 MMUAccessType access_type,
/openbmc/qemu/target/mips/sysemu/
H A Dphysaddr.c80 MMUAccessType access_type, int mmu_idx, in get_seg_physical_address() argument
93 access_type); in get_seg_physical_address()
104 MMUAccessType access_type, int mmu_idx, in get_segctl_physical_address() argument
112 access_type, mmu_idx, am, eu, segmask, in get_segctl_physical_address()
118 MMUAccessType access_type, int mmu_idx) in get_physical_address() argument
143 real_address, access_type, in get_physical_address()
150 real_address, access_type); in get_physical_address()
159 real_address, access_type); in get_physical_address()
186 real_address, access_type, in get_physical_address()
200 real_address, access_type); in get_physical_address()
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/openbmc/qemu/target/arm/tcg/
H A Dtlb_helper.c172 MMUAccessType access_type, in arm_deliver_fault() argument
187 bool is_vncr = (access_type != MMU_INST_FETCH) && in arm_deliver_fault()
201 access_type == MMU_INST_FETCH, in arm_deliver_fault()
204 access_type == MMU_DATA_STORE, fsc); in arm_deliver_fault()
245 if (access_type == MMU_INST_FETCH) { in arm_deliver_fault()
250 same_el, access_type == MMU_DATA_STORE, in arm_deliver_fault()
252 if (access_type == MMU_DATA_STORE in arm_deliver_fault()
267 MMUAccessType access_type, in arm_cpu_do_unaligned_access() argument
277 arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); in arm_cpu_do_unaligned_access()
306 MMUAccessType access_type, in arm_cpu_do_transaction_failed() argument
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/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training.c93 static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type,
101 int adll_calibration(u32 dev_num, enum hws_access_type access_type,
103 static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type,
346 enum hws_access_type access_type = ACCESS_TYPE_UNICAST; in hws_ddr3_tip_init_controller() local
399 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
405 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
410 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
415 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
426 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
431 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
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H A Dddr3_training_bist.c13 enum hws_access_type access_type,
21 enum hws_access_type access_type, u32 if_num, in ddr3_tip_bist_activate() argument
34 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, in ddr3_tip_bist_activate()
39 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, in ddr3_tip_bist_activate()
44 ddr3_tip_load_pattern_to_odpg(0, access_type, 0, pattern, offset); in ddr3_tip_bist_activate()
46 …ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_BUFFER_SIZE_REG, pattern_addr_length, MASK_ALL_BITS… in ddr3_tip_bist_activate()
51 ddr3_tip_configure_odpg(0, access_type, 0, dir, in ddr3_tip_bist_activate()
56 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_BUFFER_OFFS_REG, offset, MASK_ALL_BITS); in ddr3_tip_bist_activate()
59 ddr3_tip_bist_operation(0, access_type, 0, BIST_STOP); in ddr3_tip_bist_activate()
61 ddr3_tip_bist_operation(0, access_type, 0, BIST_START); in ddr3_tip_bist_activate()
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H A Dddr3_training_ip_engine.c336 int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type, in ddr3_tip_ip_training() argument
379 (dev_num, access_type, interface_num, in ddr3_tip_ip_training()
383 (dev_num, access_type, interface_num, in ddr3_tip_ip_training()
388 (dev_num, access_type, interface_num, in ddr3_tip_ip_training()
392 (dev_num, access_type, interface_num, in ddr3_tip_ip_training()
398 ddr3_tip_load_pattern_to_odpg(dev_num, access_type, interface_num, in ddr3_tip_ip_training()
406 (dev_num, access_type, interface_num, direction, in ddr3_tip_ip_training()
414 (dev_num, access_type, interface_num, in ddr3_tip_ip_training()
437 (dev_num, access_type, interface_num, in ddr3_tip_ip_training()
444 (dev_num, access_type, interface_num, OPCODE_REG0_REG(1), in ddr3_tip_ip_training()
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/openbmc/linux/kernel/kcsan/
H A Dreport.c32 int access_type; member
433 get_bug_type(ai->access_type | other_info->ai.access_type), in print_report()
437 pr_err("BUG: KCSAN: %s in %pS\n", get_bug_type(ai->access_type), in print_report()
446 get_access_type(other_info->ai.access_type), other_info->ai.ptr, in print_report()
459 get_access_type(ai->access_type), ai->ptr, ai->size, in print_report()
463 get_access_type(ai->access_type), ai->ptr, ai->size, in print_report()
638 int access_type, unsigned long ip) in prepare_access_info() argument
643 .access_type = access_type, in prepare_access_info()
647 .ip = (access_type & KCSAN_ACCESS_SCOPED) ? ip : 0, in prepare_access_info()
651 void kcsan_report_set_info(const volatile void *ptr, size_t size, int access_type, in kcsan_report_set_info() argument
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/openbmc/qemu/target/i386/tcg/sysemu/
H A Dexcp_helper.c33 MMUAccessType access_type; member
146 const MMUAccessType access_type = in->access_type; in mmu_translate() local
404 if ((pkr_prot & (1 << access_type)) == 0) { in mmu_translate()
410 if ((prot & (1 << access_type)) == 0) { in mmu_translate()
417 if (access_type == MMU_DATA_STORE) { in mmu_translate()
447 flags = probe_access_full_mmu(env, paddr, 0, access_type, in mmu_translate()
462 if ((prot & (1 << access_type)) == 0) { in mmu_translate()
492 assert(access_type != MMU_INST_FETCH); in mmu_translate()
501 switch (access_type) { in mmu_translate()
544 MMUAccessType access_type, int mmu_idx, in get_physical_address() argument
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/openbmc/qemu/include/hw/core/
H A Dtcg-cpu-ops.h89 MMUAccessType access_type,
113 MMUAccessType access_type, uintptr_t ra);
158 MMUAccessType access_type, int mmu_idx,
168 MMUAccessType access_type, int mmu_idx,
175 unsigned size, MMUAccessType access_type,
183 MMUAccessType access_type,
/openbmc/qemu/target/m68k/
H A Dhelper.c681 int access_type) in check_TTR() argument
694 if ((access_type & ACCESS_SUPER) != 0) { in check_TTR()
700 if ((access_type & ACCESS_SUPER) == 0) { in check_TTR()
729 int access_type, target_ulong *page_size) in get_physical_address() argument
735 bool debug = access_type & ACCESS_DEBUG; in get_physical_address()
742 if (check_TTR(env->mmu.TTR(access_type, i), in get_physical_address()
743 prot, address, access_type)) { in get_physical_address()
744 if (access_type & ACCESS_PTEST) { in get_physical_address()
756 if (access_type & ACCESS_CODE) { in get_physical_address()
759 if (access_type & ACCESS_SUPER) { in get_physical_address()
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/openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/fpga/
H A Dsdk.c125 void *buf, enum mlx5_fpga_access_type access_type) in mlx5_fpga_mem_read() argument
129 switch (access_type) { in mlx5_fpga_mem_read()
137 access_type); in mlx5_fpga_mem_read()
146 void *buf, enum mlx5_fpga_access_type access_type) in mlx5_fpga_mem_write() argument
150 switch (access_type) { in mlx5_fpga_mem_write()
158 access_type); in mlx5_fpga_mem_write()
/openbmc/qemu/target/microblaze/
H A Dhelper.c30 MMUAccessType access_type) in mb_cpu_access_is_secure() argument
32 if (access_type == MMU_INST_FETCH) { in mb_cpu_access_is_secure()
40 MMUAccessType access_type, int mmu_idx, in mb_cpu_tlb_fill() argument
50 attrs.secure = mb_cpu_access_is_secure(cpu, access_type); in mb_cpu_tlb_fill()
61 hit = mmu_translate(cpu, &lu, address, access_type, mmu_idx); in mb_cpu_tlb_fill()
84 env->esr = access_type == MMU_INST_FETCH ? 17 : 16; in mb_cpu_tlb_fill()
85 env->esr |= (access_type == MMU_DATA_STORE) << 10; in mb_cpu_tlb_fill()
88 env->esr = access_type == MMU_INST_FETCH ? 19 : 18; in mb_cpu_tlb_fill()
89 env->esr |= (access_type == MMU_DATA_STORE) << 10; in mb_cpu_tlb_fill()
272 MMUAccessType access_type, in mb_cpu_do_unaligned_access() argument
/openbmc/qemu/target/i386/tcg/user/
H A Dexcp_helper.c26 MMUAccessType access_type, in x86_cpu_record_sigsegv() argument
40 env->error_code = ((access_type == MMU_DATA_STORE) << PG_ERROR_W_BIT) in x86_cpu_record_sigsegv()
53 MMUAccessType access_type, uintptr_t ra) in x86_cpu_record_sigbus() argument
56 handle_unaligned_access(&cpu->env, addr, access_type, ra); in x86_cpu_record_sigbus()
/openbmc/qemu/target/loongarch/
H A Dcpu_helper.c17 int access_type, int index, int mmu_idx) in loongarch_map_tlb_entry() argument
55 if (access_type == MMU_INST_FETCH && tlb_nx) { in loongarch_map_tlb_entry()
59 if (access_type == MMU_DATA_LOAD && tlb_nr) { in loongarch_map_tlb_entry()
68 if ((access_type == MMU_DATA_STORE) && !tlb_d) { in loongarch_map_tlb_entry()
146 MMUAccessType access_type, int mmu_idx) in loongarch_map_address() argument
153 address, access_type, index, mmu_idx); in loongarch_map_address()
161 MMUAccessType access_type, int mmu_idx) in loongarch_map_address() argument
181 MMUAccessType access_type, int mmu_idx) in get_physical_address() argument
225 access_type, mmu_idx); in get_physical_address()
/openbmc/qemu/target/i386/tcg/
H A Dhelper-tcg.h73 MMUAccessType access_type,
77 MMUAccessType access_type,
80 MMUAccessType access_type, uintptr_t ra);
83 MMUAccessType access_type, int mmu_idx,
86 MMUAccessType access_type,
/openbmc/qemu/target/alpha/
H A Dmem_helper.c43 MMUAccessType access_type, uintptr_t retaddr) in alpha_cpu_record_sigbus() argument
49 MMUAccessType access_type, in alpha_cpu_do_unaligned_access() argument
62 MMUAccessType access_type, in alpha_cpu_do_transaction_failed() argument
69 env->trap_arg1 = access_type == MMU_DATA_STORE ? 1 : 0; in alpha_cpu_do_transaction_failed()
/openbmc/linux/tools/testing/selftests/powerpc/mm/
H A Dstack_expansion_ldst.c31 enum access_type { enum
42 int consume_stack(unsigned long target_sp, unsigned long stack_high, int delta, enum access_type ty… in consume_stack()
114 int child(unsigned int stack_used, int delta, enum access_type type) in child()
129 static int test_one(unsigned int stack_used, int delta, enum access_type type) in test_one()
157 static void test_one_type(enum access_type type, unsigned long page_size, unsigned long rlim_cur) in test_one_type()
/openbmc/qemu/target/mips/tcg/
H A Dtcg-internal.h22 MMUAccessType access_type, int mmu_idx,
56 MMUAccessType access_type, uintptr_t retaddr);
59 MMUAccessType access_type,
65 MMUAccessType access_type, int mmu_idx,
/openbmc/qemu/accel/tcg/
H A Dcputlb.c103 MMUAccessType access_type) in tlb_read_idx() argument
115 const uint32_t *ptr = (uint32_t *)&entry->addr_idx[access_type]; in tlb_read_idx()
119 const uint64_t *ptr = &entry->addr_idx[access_type]; in tlb_read_idx()
1014 MMUAccessType access_type, bool enable) in tlb_set_compare() argument
1026 ent->addr_idx[access_type] = address; in tlb_set_compare()
1027 full->slow_flags[access_type] = flags; in tlb_set_compare()
1256 MMUAccessType access_type, in cpu_unaligned_access() argument
1259 cpu->cc->tcg_ops->do_unaligned_access(cpu, addr, access_type, in cpu_unaligned_access()
1282 unsigned size, MMUAccessType access_type, int mmu_idx, in io_failed() argument
1290 access_type, mmu_idx, in io_failed()
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/openbmc/qemu/target/arm/
H A Dptw.c78 MMUAccessType access_type, MemOp memop,
84 MMUAccessType access_type, MemOp memop,
1014 uint32_t address, MMUAccessType access_type, in get_phys_addr_v5() argument
1124 if (!(result->f.prot & (1 << access_type))) { in get_phys_addr_v5()
1138 uint32_t address, MMUAccessType access_type, in get_phys_addr_v6() argument
1278 if (!(result->f.prot & (1 << access_type))) { in get_phys_addr_v6()
1685 MMUAccessType access_type, MemOp memop, in get_phys_addr_lpae() argument
1713 access_type != MMU_INST_FETCH, in get_phys_addr_lpae()
1980 && access_type == MMU_DATA_STORE) { in get_phys_addr_lpae()
2158 if (!(result->f.prot & (1 << access_type))) { in get_phys_addr_lpae()
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