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Searched refs:XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dxusb-padctl.c25 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1) macro
193 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; in pcie_phy_enable()
215 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; in pcie_phy_disable()
/openbmc/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra-xusb.c33 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1) macro
575 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; in pcie_phy_power_on()
599 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; in pcie_phy_power_off()
/openbmc/linux/drivers/phy/tegra/
H A Dxusb-tegra124.c57 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1) macro
1102 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; in tegra124_pcie_phy_power_on()
1135 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; in tegra124_pcie_phy_power_off()