Searched refs:XEHP_L3SQCREG5 (Results 1 – 2 of 2) sorted by relevance
1041 #define XEHP_L3SQCREG5 MCR_REG(0xb158) macro
686 wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, in dg2_ctx_gt_tuning_init()