Home
last modified time | relevance | path

Searched refs:XCHAL_TRAX_MEM_SHAREABLE (Results 1 – 10 of 10) sorted by relevance

/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h438 #define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ macro
/openbmc/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dcore.h496 #define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ macro
/openbmc/linux/arch/xtensa/variants/de212/include/variant/
H A Dcore.h560 #define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ macro
/openbmc/linux/arch/xtensa/variants/csp/include/variant/
H A Dcore.h539 #define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ macro
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h538 #define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dcore.h538 #define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ macro
/openbmc/linux/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dcore.h539 #define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ macro
/openbmc/qemu/target/xtensa/core-de212/
H A Dcore-isa.h574 #define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ macro
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h595 #define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ macro
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h677 #define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ macro