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Searched refs:XCHAL_HAVE_ACELITE (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/xtensa/core-de212/
H A Dcore-isa.h256 #define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ macro
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h271 #define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ macro
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h349 #define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ macro