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Searched refs:XCHAL_DCACHE_IS_COHERENT (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/arch/xtensa/variants/de212/include/variant/
H A Dcore.h217 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
273 XCHAL_DCACHE_IS_COHERENT || \
/openbmc/linux/arch/xtensa/variants/csp/include/variant/
H A Dcore.h217 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
273 XCHAL_DCACHE_IS_COHERENT || \
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h217 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
273 XCHAL_DCACHE_IS_COHERENT || \
/openbmc/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dcore.h195 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
251 XCHAL_DCACHE_IS_COHERENT || \
/openbmc/linux/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dcore.h218 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
274 XCHAL_DCACHE_IS_COHERENT || \
/openbmc/linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
H A Dcore.h138 #define XCHAL_DCACHE_IS_COHERENT 1 /* MP coherence feature */ macro
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h165 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
/openbmc/qemu/target/xtensa/core-lx106/
H A Dcore-isa.h158 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h189 #define XCHAL_DCACHE_IS_COHERENT 1 /* MP coherence feature */ macro
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dcore-isa.h168 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/
H A Dcore.h147 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
/openbmc/linux/arch/xtensa/variants/dc233c/include/variant/
H A Dcore.h169 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
/openbmc/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dcore.h189 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
/openbmc/linux/arch/xtensa/include/asm/
H A Dinitialize_mmu.h48 #if XCHAL_DCACHE_IS_COHERENT
/openbmc/qemu/target/xtensa/core-de212/
H A Dcore-isa.h226 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h240 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h291 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro